C8051F996DK Silicon Laboratories Inc, C8051F996DK Datasheet - Page 223

• Manufacturer Part Number: C8051F996DK
• Description: KIT DEV FOR C8051F996
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F996DK

• Contents: Board, Batteries, Cables, CDs, Debug Adapter, Documentation, Power Adapter
• Processor To Be Evaluated: C8051F996
• Processor Series: C8051F98x
• Interface Type: USB
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F996
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1963

21.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section “13. Interrupt Handler” on page 137 and Section “15. Power Management” on page 161 for
more details on interrupt and wake-up sources.
SFR Definition 21.4. P0MASK: Port0 Mask Register
SFR Page= 0x0; SFR Address = 0xC7
SFR Definition 21.5. P0MAT: Port0 Match Register
SFR Page= 0x0; SFR Address = 0xD7
Name
Reset
Name
Reset
Type
Type
7:0
7
Bit
Bit
Bit
Bit
:
0
P0MAT[7:0] Port 0 Match Value.
P0MASK[7:0] Port0 Mask Value.
Name
Name
7
0
7
1
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
Selects the P0 pins to be compared with the corresponding bits in P0MAT.
0: P0.n pin pad logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin pad logic value is compared to P0MAT.n.
6
0
6
1
5
0
5
1
Rev. 1.0
P0MASK[7:0]
4
0
4
1
P0MAT[7:0]
R/W
R/W
C8051F99x-C8051F98x
Function
Function
3
0
3
1
2
0
2
1
1
0
1
1
0
0
0
1
223