EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 55

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

PULSE-WIDTH MODULATOR (PWM)
The PWM on the ADuC832 is a highly flexible PWM offering
programmable resolution and an input clock, and can be confi-
gured for any one of six different modes of operation. Two of
these modes allow the PWM to be configured as a Σ-Δ DAC
with up to 16 bits of resolution. A block diagram of the PWM
is shown in Figure 56.
T0/EXTERNAL PWM CLOCK
The PWM uses five SFRs: the control SFR (PWMCON) and
four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L).
PWMCON (as described in Table 27) controls the different
modes of operation of the PWM as well as the PWM clock
frequency. PWM0H/PWM0L and PWM1H/PWM1L are the data
Table 27. PWMCON SFR Bit Designations
Bit
[7]
[6:4]
[3:2]
[1:0]
Name
SNGL
MD[2:0]
CDIV[1:0]
CSEL[1:0]
f
XTAL
f
f
XTAL
VCO
/15
Figure 56. PWM Block Diagram
Description
Turns off PWM output at P2.6 or P3.4, leaving port pin free for digital I/O.
PWM mode bits. The MD[2:0] bits choose the PWM mode as follows:
MD2
0
0
0
0
1
1
1
1
PWM clock divider. These bits scale the clock source for the PWM counter as follows:
CDIV1
0
0
1
1
PWM clock divider. These bits select the clock source for the PWM as follows:
CSEL1
0
0
1
1
SELECT
CLOCK
MODE
16-BIT PWM COUNTER
PROGRAMMABLE
COMPARE
PWM0H/L
DIVIDER
MD1
0
0
1
1
0
0
1
1
CDIV0
0
1
0
1
CSEL0
0
1
0
1
PWM1H/L
MD0
0
1
0
1
0
1
0
1
PWM Counter
Selected clock/1
Selected clock/4
Selected clock/16
Selected clock/64
PWM Clock
f
f
External input at P3.4/T0
f
XTAL
XTAL
VCO
/15
= 16.78 MHz
P2.6
P2.7
Rev. A | Page 55 of 92
Mode 1: single variable resolution PWM on P2.7 or P3.3
Mode 2: twin 8-bit PWM
Mode 3: twin 16-bit PWM
Mode 4: dual NRZ 16-bit Σ-Δ DAC
Mode 5: dual 8-bit PWM
Mode 6: dual RZ 16-bit Σ-Δ DAC
Reserved for future use
Mode
Mode 0: PWM disabled
registers that determine the duty cycles of the PWM outputs. The
output pins that the PWM uses are determined by the CFG832
register, and can be either P2.6 and P2.7 or P3.4 and P3.3. In
this section of the data sheet, it is assumed that P2.6 and P2.7
are selected as the PWM outputs.
To use the PWM user software, first write to PWMCON to
select the PWM mode of operation and the PWM input clock.
Writing to PWMCON also resets the PWM counter. In any of
the 16-bit modes of operation (Mode 1, Mode 3, Mode 4, and
Mode 6), user software should write to the PWM0L or PWM1L
SFR first. This value is written to a hidden SFR. Writing to the
PWM0H or PWM1H SFRs updates both the PWMxH and the
PWMxL SFRs but does not change the outputs until the end of
the PWM cycle in progress. The values written to these 16-bit
registers are then used in the next PWM cycle.
PWMCON (PWM CONTROL SFR)
SFR Address:
Power-On Default Value:
Bit Addressable:
AEH
00H
No
ADuC832