C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 210
![BOARD PROTOTYPE W/C8051F560](/photos/9/25/92557/c8051f560-tb_sml.jpg)
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
- Current page: 210 of 302
- Download datasheet (3Mb)
C8051F55x/56x/57x
The CAN controller clock must be less than or equal to 25 MHz. If the CIP-51 system clock is above
25 MHz, the divider in the CAN0CFG register must be set to divide the CAN controller clock down to an
appropriate speed.
21.1.2. CAN Register Access
The CAN controller clock divider selected in the CAN0CFG SFR affects how the CAN registers can be
accessed. If the divider is set to 1, then a CAN SFR can immediately be read after it is written. If the divider
is set to a value other than 1, then a read of a CAN SFR that has just been written must be delayed by a
certain number of cycles. This delay can be performed using a NOP or some other instruction that does
not attempt to read the register. This access limitation applies to read and read-modify-write instructions
that occur immediately after a write. The full list of affected instructions is ANL, ORL, MOV, XCH, and XRL.
For example, with the CAN0CFG divider set to 1, the CAN0CN SFR can be accessed as follows:
MOV CAN0CN, #041
MOV R7, CAN0CN
With the CAN0CFG divider set to /2, the same example code requires an additional NOP:
MOV CAN0CN, #041
NOP
MOV R7, CAN0CN
The number of delay cycles required is dependent on the divider setting. With a divider of 2, the read must
wait for 1 system clock cycle. With a divider of 4, the read must wait 3 system clock cycles, and with the
divider set to 8, the read must wait 7 system clock cycles. The delay only needs to be applied when read-
ing the same register that was written. The application can write and read other CAN SFRs without any
delay.
21.1.3. Example Timing Calculation for 1 Mbit/Sec Communication
This example shows how to configure the CAN controller timing parameters for a 1 Mbit/Sec bit rate.
Table 21.1 shows timing-related system parameters needed for the calculation.
Each bit transmitted on a CAN network has 4 segments (Sync_Seg, Prop_Seg, Phase_Seg1, and
Phase_Seg2), as shown in Figure 18.3. The sum of these segments determines the CAN bit time (1/bit
rate). In this example, the desired bit rate is 1 Mbit/sec; therefore, the desired bit time is 1000 ns.
210
CIP-51 system clock (SYSCLK)
CAN controller clock (f
CAN clock period (t
CAN time quantum (t
CAN bus length
Propogation delay time
Notes:
1. The CAN time quantum is the smallest unit of time recognized by the CAN controller. Bit timing parameters
2. The Baud Rate Prescaler (BRP) is defined as the value of the BRP Extension Register plus 1. The BRP
3. Based on an ISO-11898 compliant transceiver. CAN does not specify a physical layer.
are specified in integer multiples of the time quantum.
extension register has a reset value of 0x0000. The BRP has a reset value of 1.
Parameter
sys
q
)
)
sys
3
)
Table 21.1. Background System Information
; Enable access to Bit Timing Register
; Copy CAN0CN to R7
; Enable access to Bit Timing Register
; Wait for write to complete
; Copy CAN0CN to R7
41.667 ns
41.667 ns
24 MHz
24 MHz
400 ns
Value
10 m
Rev. 1.1
Internal Oscillator Max
CAN0CFG divider set to 1
Derived from 1/f
Derived from t
5 ns/m signal delay between CAN nodes
2 x (transceiver loop delay + bus line delay)
sys
sys
x BRP
Description
1,2
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