C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 70
![BOARD PROTOTYPE W/C8051F560](/photos/9/25/92557/c8051f560-tb_sml.jpg)
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
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C8051F55x/56x/57x
8. Comparators
The C8051F55x/56x/57x devices include two on-chip programmable voltage Comparators. A block dia-
gram of the comparators is shown in Figure 8.1, where “n” is the comparator number (0 or 1). The two
Comparators operate identically except that Comparator0 can also be used a reset source. For input
selection details, refer to SFR Definition 8.5 and SFR Definition 8.6.
Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “19.4. Port I/O Initialization” on page 172). Comparator0 may also be used as a
reset source (see Section “16.5. Comparator0 Reset” on page 140).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 8.5). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 8.6). The CMX1P1-
CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1
negative input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “19.1. Port I/O Modes of Operation” on page 168).
70
Comparator
Input Mux
CPTnMD
Figure 8.1. Comparator Functional Block Diagram
CPn +
CPn -
+
-
CPTnCN
GND
VIO
CPnRIF
CPnFIF
Decision
Reset
Tree
Rev. 1.1
(SYNCHRONIZER)
D
SET
CLR
Q
Q
0
1
0
1
D
SET
CLR
Q
Q
CPnEN
Crossbar
0
1
EA
0
1
CPnA
Interrupt
CPn
CPn
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