ISL6323EVAL1Z Intersil, ISL6323EVAL1Z Datasheet
ISL6323EVAL1Z
Specifications of ISL6323EVAL1Z
Related parts for ISL6323EVAL1Z
ISL6323EVAL1Z Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 All other trademarks mentioned are the property of their respective owners. ISL6323 Hybrid SVI/PVI FN9278.4 | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved ...
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Pinout FB_NB 1 ISEN_NB+ 2 RGND_NB 3 VID0/VFIXEN 4 VID1/SEL 5 VID2/SVD 6 7 VID3/SVC 8 VID4 9 VID5 10 VCC RGND Integrated Driver Block Diagram PWM SOFT-START AND CONTROL FAULT LOGIC 2 ISL6323 ISL6323 ISL6323 (48 ...
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Controller Block Diagram NB_REF NB_CS ISEN_NB+ CURRENT SENSE ISEN_NB- VDDPWRGD APA APA COMP OFFSET OFS FB E/A DVC 2X ∑ RGND PWROK VID0/VFIXEN SVI VID1/SEL SLAVE BUS VID2/SVD AND VID3/SVC PVI DAC VID4 VID5 NB_REF OV LOGIC VSEN UV LOGIC ...
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Typical Application - SVI Mode FB VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 VCC BOOT2 OFS UGATE2 FS PHASE2 LGATE2 RSET VFIXEN ISEN2- SEL ISEN2+ SVD SVC RGND VID4 NC VID5 NC ...
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Typical Application - PVI Mode FB VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 VCC BOOT2 OFS UGATE2 FS PHASE2 LGATE2 RSET VID0 ISEN2- VID1/SEL ISEN2+ VID2 VID3 RGND VID4 VID5 NC PWROK ...
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... Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C = 12V) Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below BOOT-PHASE - 0. 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp BOOT + 0.3V BOOT Recommended Operating Conditions VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature ISL6323CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° ...
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Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER PIN_ADJUSTABLE OFFSET OFS ...
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Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER OVERVOLTAGE PROTECTION OVP ...
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Functional Pin Description VID1/SEL This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling the ISL6323. If the pin is LO prior to enable, the ISL6323 is in SVI mode and the ...
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... MOSFETs’ gates. PWM3 and PWM4 Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil driver 4-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to disable them and configure the core VR controller for 2-phase or 3-phase operation ...
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MOSFET has turned off. Operation The ISL6323 utilizes a multiphase architecture to provide a low cost, space saving power conversion solution for the processor core voltage. The controller also implements a simple ...
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... FS pin and ground. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal has transitioned high ...
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The PWM signals command the MOSFET driver to turn on/off the channel MOSFETs. For 4-channel operation, the channel firing order is 4-3-2-1: PWM3 pulse happens 1 cycle after PWM4, PWM2 output follows another 1 cycle ...
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... Channel-current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current balance method is illustrated in Figure 6, with error 14 ISL6323 correction for Channel 1 represented ...
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TABLE 1. 6-BIT PARALLEL VID CODES (Continued) VID5 VID4 VID3 VID2 VID1 ...
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PRE-PWROK METAL VID Typical motherboard start-up occurs with the VFIXEN input low. The controller decodes the SVC and SVD inputs to determine the Pre-PWROK metal VID setting. Once the POR circuitry is satisfied, the ISL6323 begins decoding the inputs per ...
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... OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6323 to include the combined tolerances of each of these elements. The output of the error amplifier, V COMP modulator to generate the PWM signals ...
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EXTERNAL CIRCUIT ISL6323 INTERNAL CIRCUIT FS R DROOP FS CONTROL COMP DROOP OFS - ∑ VSEN + + V OUT RGND - FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE ...
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V OUT + V R OFS FB VREF - FB I OFS OFS ISL6323 R OFS GND FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE PROGRAMMING Dynamic VID The AMD processor does not step the output voltage commands up or down to ...
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... PVCC1_2 ISL6323 becomes enabled. The schematic in Figure 12 demonstrates sequencing the ISL6323 with the ISL66xx PVCC_NB family of Intersil MOSFET drivers, which require 12V bias. +12V When selecting the value of the resistor divider the driver maximum rising POR threshold should be used for 10.7kΩ ...
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Operation” on page 12 for details). If Channel 4 and/or Channel 3 are disabled, then the corresponding PWMn and ISENn+ pins may be left unconnected. Soft-Start Output Voltage Targets ...
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REPEAT FOR EACH - 100µA CORE CHANNEL OCP + ONLY SOFT-START, FAULT AND CONTROL LOGIC DUPLICATED FOR + NB AND CORE 1.8V OVP - + DAC + 250mV VSEN UV + DAC - 300mV ...
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Balance” on page 14 for more detail on how the average current is measured. Once the average current exceeds 100µA, a comparator triggers the converter to begin overcurrent protection procedures. The Core regulator and the ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications ...
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Finally, the resistive part of the upper MOSFET is given in Equation UP( ⎛ ⎞ ≈ ⋅ M ⋅ P-P ⎜ ⎟ --------- - ----- - UP 4 ...
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The I *VCC product is the Q quiescent power of the controller without load on the drives. BOOT PVCC R HI1 G UGATE R LO1 R G1 PHASE FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH PVCC ...
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Calculate the values for R and R 1 Equations 35 and 36 will allow for their computation Core K ---------------------------------------------- = Core Core ⋅ Core Core Core ...
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Inductor DCR Current Sensing Component Fine Tuning V IN UGATE(n) MOSFET DRIVER LGATE(n) INDUCTOR R ISL6323 INTERNAL CIRCUIT I n SAMPLE + V ( ISEN I SEN { TO ACTIVE CORE CHANNELS TO NORTH BRIDGE FIGURE ...
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C (OPTIONAL COMP VSEN FIGURE 22. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6323 CIRCUIT Since the system poles and zero are affected by the values of the components that are meant to compensate ...
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C ESR ⋅ ------------------------------------------- - ⋅ ⋅ ESR – ⋅ ⋅ ESR – ------------------------------------------- - ⋅ 0. ---------------------------------------------------------------------------------------------------- ...
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The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV . This places an upper limit on inductance. MAX Equation 56 gives the ...
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L(P-P) L(P- 0. L(P-P) O L(P-P) 0.2 0 0.2 0.4 0.6 DUTY CYCLE (V FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER 0.3 0.2 0 ...
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VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 R APA C APA LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 C C FILTER VCC OFS BOOT2 R OFS UGATE2 FS PHASE2 R ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 35 ...