PIC18F66J11-I/PT Microchip Technology, PIC18F66J11-I/PT Datasheet
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... Microchip Technology Inc. PIC18F87J11 Family 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology Data Sheet DS39778D ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... C™ Master and Slave modes • Two Enhanced USART modules: - Supports RS-485, RS-232 and LIN 1.2 - Auto-wake-up on Start bit - Auto-Baud Detect Flash SRAM Program Data Device Memory Memory (bytes) (bytes) PIC18F66J11 64 kB 3930 PIC18F66J16 96 kB 3930 PIC18F67J11 128 kB 3930 PIC18F86J11 64 kB 3930 PIC18F86J16 96 kB ...
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... RF5/AN10/C1INB/CV 13 REF RF4/AN9/C2INA 14 RF3/AN8/C2INB 15 RF2/PMA5/AN7/C1OUT 16 Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting. DS39778D-page PIC18F6XJ11 PIC18F6XJ16 RB0/INT0/FLT0 48 RB1/INT1/PMA4 47 46 RB2/INT2/PMA3 45 RB3/INT3/PMA2 44 RB4/KBI0/PMA1 43 RB5/KBI1/PMA0 42 RB6/KBI2/PGC OSC2/CLKO/RA6 39 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO1 36 35 RC4/SDI1/SDA1 34 RC3/SCK1/SCL1 33 RC2/ECCP1/P1A 31 32 © 2009 Microchip Technology Inc. ...
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... The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings. 2: P1B, P1C, P3B, and P3C pin placement depends on the ECCPMX Configuration bit setting. 3: PMP pin placement depends on the PMPMX Configuration bit setting. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY ...
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... Electrical Characteristics .......................................................................................................................................................... 385 28.0 Packaging Information.............................................................................................................................................................. 425 Appendix A: Revision History............................................................................................................................................................. 431 Appendix B: Device Differences......................................................................................................................................................... 431 The Microchip Web Site ..................................................................................................................................................................... 433 Customer Change Notification Service .............................................................................................................................................. 433 Customer Support .............................................................................................................................................................................. 433 Reader Response .............................................................................................................................................................................. 434 Product Identification System............................................................................................................................................................. 447 DS39778D-page 6 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY DS39778D-page 7 ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 8 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F66J11 • PIC18F86J11 • PIC18F66J16 • PIC18F86J16 • PIC18F67J11 • PIC18F87J11 This family introduces a line of low-voltage, general purpose microcontrollers with the main traditional advantage of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – ...
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... A/D input channels (11 on 64-pin devices 80-pin devices). All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. 2 C™ © 2009 Microchip Technology Inc. ...
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... I/O Ports Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY PIC18F66J11 PIC18F66J16 DC – 48 MHz DC – 48 MHz 64K 96K 32768 49152 3930 3930 29 Ports ...
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... Timer4 CCP4 CCP5 EUSART2 EUSART1 PORTA Data Latch (1) RA0:RA7 (2.0, 3.9 Kbytes) 12 PORTB (1) RB0:RB7 12 4 Access Bank 12 PORTC (1) RC0:RC7 logic PORTD (1) RD0:RD7 8 PRODH PRODL PORTE (1) RE0:RE7 Multiply PORTF 8 8 (1) RF2:RF7 ALU<8> 8 PORTG (1) RG0:RG4 Comparators MSSP1 MSSP2 © 2009 Microchip Technology Inc. ...
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... Timer0 10-Bit PMP ECCP1 ECCP2 ECCP3 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Data Latch 8 8 Data Memory (2.0, 3.9 Kbytes) PCLATU PCLATH ...
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... OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. Available only in INTIO1 and INTPLL1 Oscillator modes. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description /4). OSC ) DD © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... I/O ST Synchronous serial clock input/output for I I/O ST Digital I/O. I/O TTL Parallel Master Port data. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description 2 C mode © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog input 11. I Analog Comparator 1 input A. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. Available only in INTIO and INTPLL Oscillator modes. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V /4). OSC ) DD © 2009 Microchip Technology Inc. ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin ...
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... I/O ST In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode © 2009 Microchip Technology Inc. ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin ...
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... Synchronous serial clock input/output for I I/O ST Digital I/O. I/O TTL External memory address/data 7. I/O TTL Parallel Master Port data. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode mode © 2009 Microchip Technology Inc. ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin ...
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... Parallel Master Port address. I Analog Analog input 11. I Analog Comparator 1 input A. I/O ST Digital I/O. I/O TTL Parallel Master Port address. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode © 2009 Microchip Technology Inc. ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin ...
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... ECCP1 PWM output C. I Analog Comparator 1 input C. I/O ST Digital I/O. I/O — Parallel Master Port write strobe. I Analog Analog input 15. O — ECCP1 PWM output B. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode © 2009 Microchip Technology Inc. ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 32 © 2009 Microchip Technology Inc. ...
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... MHz Source (INTOSC) INTRC Source 31 kHz (INTRC) © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY All of these modes are selected by the user by programming the FOSC2:FOSC0 Configuration bits. In addition, PIC18F87J11 Family devices can switch between different clock sources, either under software control or automatically under certain conditions. This ...
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... Phase Locked Loop (PLL) (see Section 2.4.3 “PLL Frequency Multiplier”). (2) R/W-0 R (3) (3) IRCF0 OSTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (4) (2) (5) (1) U-1 R/W-0 R/W-0 (5) (5) — SCS1 SCS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F87J11 Family devices offer the Timer1 oscillator as a secondary oscillator source. This oscillator, in all power-managed modes, is often the time base for © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 ...
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... The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. © 2009 Microchip Technology Inc. ...
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... AN943, “Practical PIC Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table 2-2 for additional information. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Osc Type Freq ...
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... The PLL is also available to the internal oscillator block when the internal oscillator block is configured as the primary clock source. In this configuration, the PLL is enabled in software and generates a clock output MHz. The operation of INTOSC with the PLL is described in Section 2.5.2 “INTPLL Modes”. © 2009 Microchip Technology Inc. the SYSCLK ...
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... OSC1 functions as RA7 (see Figure 2-6) for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure 2-7), both for digital input and output. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY FIGURE 2-6: RA7 F ...
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... The REFOCON register is an alternate SFR, and shares the same memory address as the OSCCON register accessed by setting the ADSHR bit in the WDTCON register (WDTCON<4>). /4 clock output in certain oscilla- OSC © 2009 Microchip Technology Inc. ...
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... Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value Note 1: If ROSEL = oscillator must be configured as the default oscillator with the FOSC Configuration bits to maintain clock output during Sleep mode. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 (1) ...
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... There is a delay of interval T Table 27-12), following POR, while the controller becomes ready to execute instructions. OSC1 Pin At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level I/O pin RA6, direction controlled by TRISA<7> (parameter 38, CSD OSC2 Pin © 2009 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTRC and INTOSC postcaler (internal oscillator block). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... SEC_RUN mode is entered by setting the SCS1:SCS0 bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscilla- tor is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2) ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC block source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) T PLL 1 2 n-1 n Clock Transition OSTS Bit Set © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 50 © 2009 Microchip Technology Inc. ...
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... INTRC Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39778D-page 52 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises above V DD BOR Timer will execute the additional time delay. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY FIGURE 4- Note 1: External Power-on Reset circuit is required ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 4-5). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel PWRT T PWRT © 2009 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ): CASE 1 DD ...
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... FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY T PWRT , V RISE > 3. PWRT ): CASE ...
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... Reset. Table 4-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( POR STKPTR Register BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-- uuuu uu-- uuuu © 2009 Microchip Technology Inc. ...
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... Config. Words Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... Additional details on the device Configuration Words are provided in Section 24.1 “Configuration Bits”. TABLE 5-1: FLASH CONFIGURATION WORD FOR PIC18F87J11 FAMILY DEVICES Program Configuration Device Memory (Kbytes) PIC18F66J11 64 PIC18F86J11 PIC18F66J16 96 PIC18F86J16 PIC18F67J11 128 PIC18F87J11 © 2009 Microchip Technology Inc. Word Addresses ...
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... Address shifting disabled – external address bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ Note 1: Implemented only on 80-pin devices. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory ...
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... Yes Yes Yes (2) with Address Shifting On-Chip Memory Space 000000h On-Chip Program Memory (Top of Memory) (3) (Top of Memory Mapped to External Memory 1FFFFFh – Space (Top of Memory) 1FFFFFh Table Read Table Write From To No Access No Access Yes Yes © 2009 Microchip Technology Inc. ...
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... TOSH TOSL 00h 1Ah 34h © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP1 SP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. ...
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... Note 1: Addresses F5Ah through F5Fh are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address, or load the proper BSR value, to access these registers. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Data Memory Map ...
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... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. (2) From Opcode © 2009 Microchip Technology Inc. ...
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... This register shares the same address with another register (see Table 5-4 for alternate register). 4: The PMADDRH/L and PMDOUT1H/L register pairs share the same address. PMADDR is used in Master modes and PMDOUT1 is used in Slave modes. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral ...
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... PR2 (1) (A) MEMCON R/W-0 U-0 U-0 ADSHR — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Address Name FC2h (D) ADCON0 (A) ANCON1 FC1h (D) ADCON1 (A) ANCON0 F77h (D) PR4 (A) CVRCON U-0 U-0 — SWDTEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented. 9: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Bit 4 Bit 3 Bit 2 — ...
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... GO/DONE ADON 59, 293 0000 0000 PCFG9 PCFG8 59, 295 0000 0000 ADCS1 ADCS0 59, 294 0000 0000 PCFG1 PCFG0 00-0 0000 59, 295 — SWDTEN 59, 323 0x-0 ---0 2 C™ Slave mode. See Section 19.4.3.2 © 2009 Microchip Technology Inc. ...
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... These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented. 9: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Bit 4 Bit 3 ...
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... TMR3CS TMR3ON 61, 196 0000 0000 61, 195 0000 0000 61, 196 1111 1111 CVR1 CVR0 61, 312 0000 0000 T4CKPS1 T4CKPS0 -000 0000 61, 195 2 C™ Slave mode. See Section 19.4.3.2 © 2009 Microchip Technology Inc. ...
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... These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented. 9: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Bit 4 Bit 3 ...
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... Table 25-2 and Table 25-3. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x (1) ( bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Literal Address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 “General © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Purpose Register File”), or a location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. The Access RAM bit ‘ ...
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... RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2009 Microchip Technology Inc. ...
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... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases ...
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... Figure 5-10. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 25.2.1 “Extended Instruction Syntax”. © 2009 Microchip Technology Inc. ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 000h 060h Bank 0 100h Bank 1 through ...
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... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Not Accessible Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank © 2009 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-x R/W-0 (1) FREE ...
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... Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> TBLPTRL 0 © 2009 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... The CPU will stall for duration of the erase for T (see parameter D133A Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
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... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
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... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block © 2009 Microchip Technology Inc. ...
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... MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WPROG BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 3. Set the WREN bit (EECON1<2>) to enable byte writes. 4. Disable interrupts. 5. Write 55h to EECON2. 6. Write 0AAh to EECON2. 7. Set the WR bit. This will begin the write cycle. ...
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... See Section 24.6 “Program Verification and Code Protection” for details on code protection of Flash program memory. Bit 5 Bit 4 Bit 3 Bit 2 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE TMR0IF FREE WRERR WREN Reset Bit 1 Bit 0 Values on Page INT0IF RBIF — 59 © 2009 Microchip Technology Inc. ...
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... Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
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... ADSHR bit in the Register 24-9). R/W-0 U-0 U-0 WAIT0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared WDTCON register (see R/W-0 R/W-0 WM1 WM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F87J11 FAMILY 7.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS By default, the address presented on the external bus is the value of the PC. In practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller ...
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... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. © 2009 Microchip Technology Inc. are affected; A19:A16 the ...
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... Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus ...
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... The obvious limitation to this method is that the table write must be done in pairs on a specific word even address boundary to correctly write a word location. A<20:1> 373 D<15:0> 373 cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
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... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2009 Microchip Technology Inc. ...
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... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
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... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 3Ah 55h ABh 0Eh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2009 Microchip Technology Inc. ...
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... If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 110 © 2009 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
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... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
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... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Note: Interrupt flag bits are set when an interrupt ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39778D-page 116 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 ...
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... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY U-0 R/W-0 R/W-0 — BCL1IF LVDIF U = Unimplemented bit, read as ‘ ...
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... A TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. DS39778D-page 120 R/W-0 R/W-0 R/W-0 TX2IF TMR4IF CCP5IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CCP4IF CCP3IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39778D-page 122 U-0 R/W-0 R/W-0 — BCL1IE LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
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... Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
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... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39778D-page 124 R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY U-0 R/W-1 R/W-1 — BCL1IP LVDIP U = Unimplemented bit, read as ‘0’ ...
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... Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39778D-page 126 R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CCP5IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 CCP4IP CCP3IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
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... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2009 Microchip Technology Inc. ...
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... TRIS Latch RD TRIS PORT © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
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... By default, these PMP inputs use the port’s ST buffers. As with the ODCON registers, the PADCFG1 register resides in the SFR configuration space; it shares the same memory address as the TMR2 register. PADCFG1 is accessed by setting the ADSHR bit (WDTCON<4>). © 2009 Microchip Technology Inc. 5V ...
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... Value at POR ‘1’ = Bit is set bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits 1 = Open-drain output on SDOx pin enabled 0 = Open-drain output disabled © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 CCP5OD CCP4OD ECCP3OD U = Unimplemented bit, read as ‘ ...
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... OSC INITIALIZING PORTA ; Initialize PORTA by ; clearing output ; data latches ; Alternate method to ; clear data latches ; the shared SFR ; Configure A/D ; for digital inputs ; to the shared SFR ; Value used to ; initialize ; data direction ; Set RA<3:0> as inputs, ; RA<5:4> as outputs © 2009 Microchip Technology Inc. ...
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... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate PMP configuration when the PMPMX Configuration bit is ‘0’; available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O ...
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... Values on Page: RA1 RA0 61 LATA1 LATA0 60 TRISA1 TRISA0 60 PCFG1 PCFG0 59 INITIALIZING PORTB ; Initialize PORTB by ; clearing output ; data latches ; Alternate method to clear ; output data latches ; Value used to initialize ; data direction ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs © 2009 Microchip Technology Inc. ...
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... Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin devices only). Default assignment is RC1. 2: All other pin functions are disabled when ICSP™ or ICD is enabled. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O Type ...
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... LATB1 LATB0 60 TRISB1 TRISB0 60 INT0IF RBIF 57 INT3IP RBIP 57 INT2IF INT1IF 57 INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method to clear ; output data latches ; Value used to initialize ; data direction ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs © 2009 Microchip Technology Inc. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O Description ...
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... Bit 1 Bit 0 Values on Page: RC1 RC0 61 LATC1 LATC0 60 TRISC1 TRISC0 60 INITIALIZING PORTD ; Initialize PORTD by ; clearing output ; data latches ; Alternate method to clear ; output data latches ; Value used to initialize ; data direction ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2009 Microchip Technology Inc. ...
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... Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PMP I/O. 2: Available on 80-pin devices only. 3: Default configuration for PMP (PMPMX Configuration bit = 1). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O Type O DIG LATD< ...
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... Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 LATD5 LATD4 LATD3 LATD2 TRISD5 TRISD4 TRISD3 TRISD2 (1) RJPU RG4 RG3 RG2 Description (1) (1) (1) (1) Reset Bit 1 Bit 0 Values on Page: RD1 RD0 61 LATD1 LATD0 60 TRISD1 TRISD0 60 RG1 RG0 61 © 2009 Microchip Technology Inc. ...
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... REPU (PORTG<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY PORTE is also multiplexed with Enhanced PWM outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For all devices, their default assignments are on PORTE< ...
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... External memory interface, data bit 12 input. O DIG Parallel Master Port address. O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. Description (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) © 2009 Microchip Technology Inc. ...
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... LATE LATE7 LATE6 TRISE TRISE7 TRISE6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O Type O DIG LATE<5> data output PORTE<5> data input. O DIG External memory interface, address/data bit 13 output ...
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... WDTCON,ADSHR ; Enable write/read to ; the shared SFR MOVLW C0h ; make RF1:RF2 digital MOVWF ANCON0 ; MOVLW 0Fh ; make RF<6:3> digital MOVWF ANCON1 ; BCF WDTCON,ADSHR ; Disable write/read to ; the shared SFR MOVLW CEh ; MOVWF TRISF ; Set RF5:RF4 as outputs, ; RF<7:6>,<3:1> as inputs © 2009 Microchip Technology Inc. PORTF is ...
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... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O ...
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... RF1 — 61 LATF1 — 60 TRISF1 — 60 PCFG1 PCFG0 59 PCFG9 PCFG8 59 INITIALIZING PORTG ; Initialize PORTG by ; clearing output ; data latches ; Alternate method to clear ; output data latches ; Value used to initialize ; data direction ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as outputs © 2009 Microchip Technology Inc. ...
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... O 0 Legend Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O Type DIG LATG<0> data output. ...
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... TRISG0 60 INITIALIZING PORTH ; Initialize PORTH by ; clearing output ; data latches ; Alternate method to ; clear output latches ; the shared SFR ; Configure PORTH as ; digital I/O ; the shared SFR ; Value used to initialize ; data direction ; Set RH<3:0> as inputs ; RH<5:4> as outputs ; RH<7:6> as inputs © 2009 Microchip Technology Inc. ...
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... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments are PORTE<6:3>. 2: Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O Description Type DIG LATH< ...
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... May be configured for tri-state during Enhanced PWM shutdown events. Bit 5 Bit 4 Bit 3 Bit 2 RH5 RH4 RH3 RH2 LATH5 LATH4 LATH3 LATH2 TRISH5 TRISH4 TRISH3 TRISH2 PCFG13 PCFG12 PCFG11 PCFG10 Description Reset Bit 1 Bit 0 Values on Page: RH1 RH0 60 LATH1 LATH0 61 TRISH1 TRISH0 60 PCFG9 PCFG8 59 © 2009 Microchip Technology Inc. ...
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... This occurs automatically when the interface is enabled by clearing the EBDIS control bit (MEMCON<7>). The TRISJ bits are also overridden. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Each of the PORTJ pins has a weak internal pull-up. A single control bit can turn off all the pull-ups. This is performed by clearing bit RJPU (PORTG< ...
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... I/O. Bit 5 Bit 4 Bit 3 Bit 2 RJ5 RJ4 RJ3 RJ2 LATJ5 LATJ4 LATJ3 LATJ2 TRISJ5 TRISJ4 TRISJ3 TRISJ2 (1) RG4 RG3 RG2 Description Reset Bit 1 Bit 0 Values on Page: RJ1 RJ0 61 LATJ1 LATJ0 60 TRISJ1 TRISJ0 60 RG1 RG0 61 © 2009 Microchip Technology Inc. ...
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... Parallel Master Port Parallel Slave Port. FIGURE 11-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Key features of the PMP module include: • Programmable Address Lines • Two Chip Select Lines • Programmable Strobe Options - Individual Read and Write Strobes or ...
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... R/W-0 R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (Register 11-1 and registers (Register 11-3 and (Register 11-7 and R/W-0 R/W-0 PTWREN PTRDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Read strobe active-high (PMRD Read strobe active-low (PMRD) For Master mode 1 (PMMODEH<1:0> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY (1) (1) (1) R/W-0 ...
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... Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0> Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) DS39778D-page 156 R/W-0 R/W-0 R/W-0 INCM1 INCM0 MODE16 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 MODE1 MODE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O bit 5-0 PTEN13:PTEN8: PMP Address Port Enable bits 1 = PMA<13:8> function as PMP address lines 0 = PMA<13:8> function as port I/O © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘ ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R-0 R-0 — IB3F IB2F U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 PTEN1 PTEN0 bit Bit is unknown R-0 R-0 IB1F IB0F bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 3-0 OBnE: Output Buffer n Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY U-0 R-1 R-1 — ...
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... SFRs, and has the same address as the TMR2 regis- ter. PADCFG1 is accessed by setting the ADSHR bit (WDTCON<4>). Refer to Section 5.3.4.1 “Shared Address SFRs” for more information. (1) R/W-0 R/W-0 R/W-0 ADDR<13:8> Unimplemented bit, read as ‘0’ bit is cleared R/W-0 R/W-0 bit bit is unknown © 2009 Microchip Technology Inc. ...
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... LEGACY PARALLEL SLAVE PORT EXAMPLE Master PMD<7:0> PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 11.2 Slave Port Modes The primary mode of operation for the module is con- figured using the MODE1:MODE0 bits in the PMMODEH register. The setting affects whether the module acts as a slave or a master and it determines the usage of the control pins ...
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... READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUTL1 register (PMDOUTL1<7:0>) is presented onto PMD<7:0>.The timing for the control signals in Read mode is shown in Figure 11- © 2009 Microchip Technology Inc. ...
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... PMD<7:0> PMCS PMRD PMWR Data Bus Control Lines © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY is generated, and the Buffer Overflow flag bit OBUF is set. If all 4 OBxE status bits are set, then the Output Buffer Empty flag (OBE) will also be set. 11.2.2.2 ...
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... PMDOUT1L (0) 00 PMDOUT1H (1) 01 PMDOUT2L (2) 10 PMDOUT2H (3) 11 PIC18F Slave PMA<1:0> Write Read PMD<7:0> Address Address Decode Decode PMDOUT1L (0) PMCS1 PMDOUT1H (1) PMDOUT2L (2) PMRD PMDOUT2H (3) PMWR © 2009 Microchip Technology Inc. Input Register (Buffer) PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) ...
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... PMRD PMD<7:0> PMA<1:0> IBF PMPIF © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY When an output buffer is read, the corresponding OBxE bit is set. The OBE flag bit is set when all the buf- fers are empty. If any buffer is already empty (OBxE = 1), the next read to that buffer will generate an OBUF event ...
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... During the second cycle, the upper eight bits of the address are presented on the PMD<7:0> pins with the PMALH strobe active. In the event the upper address bits are configured as chip select corresponding address bits are automatically forced to ‘0’. © 2009 Microchip Technology Inc. and pins, the ...
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... PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY PMA<13:0> PMD<7:0> PMCS1 PMCS2 Address Bus ...
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... PMDIN1L register will not initiate either a read nor a write). 11.3.10.2 INTERRUPTS When the PMP module interrupt is enabled for Master mode, the module will interrupt on every completed read or write cycle; otherwise, the BUSY bit is available to query the status of the module. © 2009 Microchip Technology Inc. ...
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... READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> PMA<13:0> PMWR PMRD PMPIF BUSY FIGURE 11-13: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> Address<7:0> PMA<13:8> PMWR PMRD PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Data DS39778D-page 169 ...
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... WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMA<13:8> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> DS39778D-page 170 Data WAITE<1:0> WAITM<3:0> = 0010 Data Data WAITE<1:0> WAITM<3:0> = 0010 © 2009 Microchip Technology Inc. ...
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... PMCS2 PMCS1 PMD<7:0> Address<7:0> PMA<13:8> PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Data Data Address<15:8> Data ...
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... READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> PMA<13:0> PMWR PMRD PMBE PMPIF BUSY DS39778D-page 172 Address<15:8> Data LSB MSB LSB MSB © 2009 Microchip Technology Inc. ...
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... PMA<13:8> PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMA<13:8> PMWR PMRD PMBE PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY LSB LSB MSB MSB DS39778D-page 173 ...
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... PMRD PMBE PMALH PMALL PMPIF BUSY FIGURE 11-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY DS39778D-page 174 Address<15:8> LSB Address<15:8> LSB MSB MSB © 2009 Microchip Technology Inc. ...
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... EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC18F PMD<7:0> PMALL PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 11.4.1 MULTIPLEXED MEMORY OR PERIPHERAL Figure 11-27 demonstrates the hookup of a memory or other addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective ...
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... PM<7:0> PMA0 PMRD/PMWR PMCS DS39778D-page 176 Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> LCD Controller D<7:0> RS R/W E Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Bit 5 Bit 4 ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 178 © 2009 Microchip Technology Inc. ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
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... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TRISA6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. Note 1: These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 182 © 2009 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: Default (legacy) SFR at this address, available when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. ...
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... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TIMER1 LP OSCILLATOR C1 PIC18F87J11 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. C1 Type ( kHz 27 pF ...
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... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2009 Microchip Technology Inc. ...
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... RETURN CLRF hours RETURN © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY lowing a later Timer1 increment. This can be done by monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L reg- ister pair while the clock is low, or one-half of the period of the clock source ...
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... DS39778D-page 188 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF RC1IF TX1IF SSP1IF CCP1IF RC1IE TX1IE SSP1IE CCP1IE RC1IP TX1IP SSP1IP CCP1IP Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 57 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP TMR1CS TMR1ON 58 © 2009 Microchip Technology Inc. ...
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... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSP1IF CCP1IF TX1IE SSP1IE CCP1IE TX1IP SSP1IP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 57 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
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... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1). It also selects the clock source options for the CCP and ECCP modules ...
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... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 194 © 2009 Microchip Technology Inc. ...
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... Timer4 is off bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 16.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the ECCPx/CCPx modules. The TMR4 register is readable and writable and is cleared on any device Reset ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX2IP TMR4IP CCP5IP TX2IF TMR4IF CCP5IF TX2IE TMR4IE CCP5IE Set TMR4IF TMR4 Output (to PWM) PR4 8 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 57 CCP4IP CCP3IP 60 CCP4IF CCP3IF 60 CCP4IE CCP3IE © 2009 Microchip Technology Inc. ...
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... CCPx pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set) 11xx = PWM mode © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. The operations of PWM mode, described in Section 17.4 “ ...
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... Timer3 is used for all Capture and Compare operations for all CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. timer are in © 2009 Microchip Technology Inc. ...
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... CCP4CON<3:0> Q1:Q4 CCP5CON<3:0> CCP5 pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 17.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... Only a CCP interrupt is generated, if enabled, and the CCPxIE bit is set. Set CCP4IF Compare Output Match Logic 4 CCP4CON<3:0> T3CCP2 Set CCP5IF Compare Output Match Logic 4 CCP5CON<3:0> CCP4 pin TRIS Output Enable CCP5 pin TRIS Output Enable © 2009 Microchip Technology Inc. ...