PIC18F66J11-I/PT Microchip Technology, PIC18F66J11-I/PT Datasheet - Page 138

• Manufacturer Part Number: PIC18F66J11-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Type: FLASH
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 3.837890625KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J11 FAMILY
TABLE 10-9:
10.5
PORTD is an 8-bit wide, bidirectional port. All pins on
PORTD are digital only and tolerate voltages up to
5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD7:AD0). The TRISD bits are also
overridden.
PORTD is also multiplexed with the data functions of
the Parallel Master Port data. In this mode, Parallel
Master Port takes priority over the other digital I/O (but
not the external memory bus). This multiplexing is
available when PMPMX = 1. When the Parallel Master
Port is active, the input buffers are TTL. For more
information, refer to Section 11.0 “Parallel Master
Port”.
DS39778D-page 138
PORTC
LATC
TRISC
Note:
Name
PORTD, TRISD and
LATD Registers
These pins are configured as digital inputs
on any device Reset.
TRISC7
LATC7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
RC7
LATBC6
TRISC6
Bit 6
RC6
TRISC5
LATC5
Bit 5
RC5
LATCB4
TRISC4
Bit 4
RC4
TRISC3
LATC3
Each of the PORTD pins has a weak internal pull-up.
This is performed by clearing bit RDPU (PORTG<7>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on all device Resets.
EXAMPLE 10-4:
Bit 3
RC3
CLRF
CLRF
MOVLW
MOVWF
TRISC2
PORTD
LATD
0CFh
TRISD
LATC2
Bit 2
RC2
; Initialize PORTD by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
TRISC1
LATC1
INITIALIZING PORTD
Bit 1
RC1
© 2009 Microchip Technology Inc.
TRISC0
LATC0
Bit 0
RC0
on Page:
Values
Reset
61
60
60