PIC18F66J11-I/PT Microchip Technology, PIC18F66J11-I/PT Datasheet - Page 134

• Manufacturer Part Number: PIC18F66J11-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Type: FLASH
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 3.837890625KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J11 FAMILY
TABLE 10-5:
10.3
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. All pins on
PORTB are digital only and tolerate voltages up to
5.5V.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
This
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a)
b)
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
DS39778D-page 134
PORTA
LATA
TRISA
ANCON0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
Name
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
Clear flag bit, RBIF.
2:
interrupt
PORTB, TRISB and
LATB Registers
(2)
Implemented only in specific oscillator modes (FOSC2 Configuration bit = 0); otherwise read as ‘0’.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
TRISA7
LATA7
PCFG7
RA7
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
can
(1)
(1)
(1)
wake
TRISA6
LATA6
PCFG6
RA6
Bit 6
(1)
(1)
the
(1)
TRISA5
LATA5
device
Bit 5
RA5
—
from
TRISA4
PCFG4
LATA4
Bit 4
RA4
TRISA3
PCFG3
LATA3
assignment for ECCP2 is RE7. As with other ECCP2
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For 80-pin devices, RB3 can be configured as the
alternate peripheral pin for the ECCP2 module and
Enhanced PWM output 2A by clearing the CCP2MX
Configuration bit. This applies only to 80-pin devices
operating in Extended Microcontroller mode. If the
device is in Microcontroller mode, the alternate
configurations, the user must ensure that the TRISB<3>
bit is set appropriately for the intended operation. Ports,
RB1, RB2, RB3, RB4 and RB5, are multiplexed with
the Parallel Master Port address.
EXAMPLE 10-2:
Bit 3
RA3
CLRF
CLRF
MOVLW
MOVWF
PORTB
LATB
0CFh
TRISB
TRISA2
PCFG2
LATA2
Bit 2
RA2
; Initialize PORTB by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
TRISA1
PCFG1
INITIALIZING PORTB
LATA1
Bit 1
RA1
© 2009 Microchip Technology Inc.
TRISA0
PCFG0
LATA0
Bit 0
RA0
on Page:
Values
Reset
61
60
60
59