PIC18F66J11-I/PT Microchip Technology, PIC18F66J11-I/PT Datasheet - Page 258

• Manufacturer Part Number: PIC18F66J11-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Type: FLASH
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 3.837890625KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J11 FAMILY
19.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPxADD<5:0> and begins counting.
The SDAx pin is released (brought high) for one Baud
Rate Generator count (T
Generator times out and if SDAx is sampled high, the
SCLx pin will be deasserted (brought high). When
SCLx is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<6:0> and
begins counting. SDAx and SCLx must be sampled
high for one T
assertion of the SDAx pin (SDAx = 0) for one T
while SCLx is high. Following this, the RSEN bit
(SSPxCON2<1>) will be automatically cleared and the
Baud Rate Generator will not be reloaded, leaving the
SDAx pin held low. As soon as a Start condition is
detected on the SDAx and SCLx pins, the S bit
(SSPxSTAT<3>) will be set. The SSPxIF bit will not be
set until the Baud Rate Generator has timed out.
FIGURE 19-22:
DS39778D-page 258
Write to SSPxCON2
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
BRG
on falling edge of ninth clock,
. This action is then followed by
RSEN bit set by hardware
REPEATED START CONDITION WAVEFORM
BRG
SDAx
SCLx
occurs here:
). When the Baud Rate
end of XMIT
SDAx = 1,
SCLx (no change).
2
C logic
BRG
T
SDAx = 1,
SCLx = 1
BRG
Immediately following the SSPxIF bit getting set, the
user may write the SSPxBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
19.4.9.1
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
T
BRG
Note:
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
T
2: A bus collision during the Repeated Start
BRG
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
event is in progress, it will not take effect.
condition occurs if:
• SDAx is sampled low when SCLx
• SCLx goes low before SDAx is
At completion of Start bit,
hardware clears RSEN bit
WCOL Status Flag
S bit set by hardware
goes from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
and sets SSPxIF
Write to SSPxBUF occurs here
T
BRG
© 2009 Microchip Technology Inc.
1st bit
T
BRG