PIC18F4320-I/PT Microchip Technology, PIC18F4320-I/PT Datasheet - Page 124

• Manufacturer Part Number: PIC18F4320-I/PT
• Description: IC MCU FLASH 4KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
12.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the Clock Select
bit, TMR1CS (T1CON<1>).
FIGURE 12-1:
FIGURE 12-2:
DS39599G-page 122
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1CKI/T1OSO
T1CKI/T1OSO
Timer1 Operation
TMR1IF
Overflow
Interrupt
Flag bit
Data Bus<7:0>
Write TMR1L
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
T1OSI
T1OSI
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
8
T1OSC
High Byte
TMR1H
Timer 1
8
TMR1H
T1OSC
8
TMR1
TMR1
Oscillator
Enable
T1OSCEN
T1OSCEN
Enable
Oscillator
TMR1L
TMR1L
8
CLR
(1)
(1)
CLR
Clock
F
Internal
OSC
Clock
Internal
F
/4
TMR1ON
OSC
CCP Special Event Trigger
On/Off
TMR1CS
/4
TMR1ON
CCP Special Event Trigger
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. The TRISC1:TRISC0 values are
ignored and the pins read as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
1
0
on/off
TMR1CS
1
0
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
T1CKPS1:T1CKPS0
T1SYNC
0
1
Prescaler
1, 2, 4, 8
2
1
0
2
© 2007 Microchip Technology Inc.
Synchronized
Clock Input
Peripheral Clocks
Synchronized
Synchronize
Clock Input
Peripheral Clocks
Synchronize
det
det