PIC18F4320-I/PT Microchip Technology, PIC18F4320-I/PT Datasheet - Page 284

• Manufacturer Part Number: PIC18F4320-I/PT
• Description: IC MCU FLASH 4KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
MOVFF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
DS39599G-page 282
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
REG1
REG2
REG1
REG2
Q1
No dummy
register ‘f’
operation
Move f to f
[ label ]
0 ≤ f
0 ≤ f
(f
None
The contents of source register ‘f
are moved to destination register
‘f
anywhere in the 4096-byte data
space (000h to FFFh) and location
of destination ‘f
anywhere from 000h to FFFh.
Either source or destination can be
W (a useful special situation).
MOVFF is particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
The MOVFF instruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
The MOVFF instruction should not
be used to modify interrupt settings
while any interrupt is enabled (see
Page 87).
2
2 (3)
MOVFF
d
Read
s
(src)
read
1100
1111
’. Location of source ‘f
) → f
No
Q2
=
=
=
=
s
d
≤ 4095
≤ 4095
d
0x33
0x11
0x33,
0x33
REG1, REG2
MOVFF f
ffff
ffff
operation
Process
Data
No
Q3
d
’ can also be
ffff
ffff
s
,f
d
s
register ‘f’
operation
’ can be
(dest)
Write
No
Q4
fff
fff
f
f
s
s
d
’
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
BSR register
BSR register
Q1
Read literal
Move Literal to Low Nibble in BSR
[ label ]
0 ≤ k ≤ 255
k → BSR
None
The 8-bit literal ‘k’ is loaded into
the Bank Select Register (BSR).
1
1
MOVLB
0000
Q2
‘k’
=
=
© 2007 Microchip Technology Inc.
0x02
0x05
5
MOVLB k
0001
Process
Data
Q3
kkkk
literal ‘k’ to
Write
BSR
Q4
kkkk