PIC18F4320-I/PT Microchip Technology, PIC18F4320-I/PT Datasheet - Page 183

• Manufacturer Part Number: PIC18F4320-I/PT
• Description: IC MCU FLASH 4KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Register 17-17). When a write
occurs to SSPBUF, the Baud Rate Generator will auto-
matically begin counting. The BRG counts down to ‘0’
and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
TABLE 17-3:
© 2007 Microchip Technology Inc.
Note 1:
CY
2
C Master mode, the Baud Rate Generator (BRG)
) on the Q2 and Q4 clocks. In I
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
F
2:
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low
time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”).
BAUD RATE
2
C interface does not conform to the 400 kHz I
I
2
C CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
SCL
2
C Master mode, the
SSPM3:SSPM0
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
PIC18F2220/2320/4220/4320
Reload
Control
* 2
CLKO
Reload
(See Register 17-4,
SSPADD VALUE
17.4.7.1
When the device is operating in a power-managed
mode, the clock source to the Baud Rate Generator
may change frequency or stop, depending on the
power-managed mode and clock source selected.
In most power modes, the Baud Rate Generator
continues to be clocked but may be clocked from the
primary clock (selected in a Configuration Word), the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the internal oscillator block (one of eight frequencies
between
selected, all clocks are stopped and the Baud Rate
Generator will not be clocked.
2
BRG Down Counter
C specification (which applies to rates greater than
Mode 1000)
SSPADD<6:0>
1Fh
0Bh
18h
63h
09h
27h
02h
09h
00h
31 kHz and 8 MHz). If the Sleep mode is
Baud Rate Generation in
Power-Managed Modes
F
OSC
(2 Rollovers of BRG)
/4
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100kHz
DS39599G-page 181
F
SCL
(2)
(1)
(1)
(1)
(1)