PIC18F4320-I/PT Microchip Technology, PIC18F4320-I/PT Datasheet - Page 132

• Manufacturer Part Number: PIC18F4320-I/PT
• Description: IC MCU FLASH 4KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
14.1
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
FIGURE 14-1:
FIGURE 14-2:
DS39599G-page 130
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set TMR3IF Flag bit
on Overflow
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1OSO/
T1CKI
T1OSI
Timer3 Operation
Data Bus<7:0>
Write TMR3L
Read TMR3L
T1OSO/
T1CKI
T1OSI
TMR3IF
Overflow
Interrupt
Flag bit
TIMER3 BLOCK DIAGRAM
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
T1OSC
8
TMR3H
High Byte
T1OSC
TMR3H
Timer3
8
To Timer1 Clock Input
Enable
Oscillator
T1OSCEN
8
TMR3
TMR3L
Oscillator
Enable
T1OSCEN
(1)
8
TMR3L
CLR
(1)
Clock
F
Internal
CLR
OSC
/4
TMR3ON
F
Internal
Clock
On/Off
OSC
TMR3CS
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC1:TRISC0 value
is ignored and the pins are read as ‘0’.
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
CCP Special Event Trigger
T3CCPx
1
0
/4
TMR3ON
On/Off
T3CKPS1:T3CKPS0
TMR3CS
1
0
T3SYNC
T3CCPx
Prescaler
CCP Special Event Trigger
1, 2, 4, 8
T3CKPS1:T3CKPS0
0
1
2
T3SYNC
Prescaler
1, 2, 4, 8
0
1
© 2007 Microchip Technology Inc.
2
Peripheral Clocks
Synchronized
Clock Input
Synchronize
Synchronized
Peripheral Clocks
det
Clock Input
Synchronize
det