PIC18F4320-I/PT Microchip Technology, PIC18F4320-I/PT Datasheet - Page 31

• Manufacturer Part Number: PIC18F4320-I/PT
• Description: IC MCU FLASH 4KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.0
The PIC18F2X20 and PIC18F4X20 devices offer a total
of six operating modes for more efficient power
management (see Table 3-1). These operating modes
provide a variety of options for selective power
conservation in applications where resources may be
limited (i.e., battery-powered devices).
There are three categories of power-managed modes:
• Sleep mode
• Idle modes
• Run modes
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PIC
both offered in the PIC18F2X20/4X20 devices
(SEC_RUN and Sleep modes, respectively). However,
additional power-managed modes are available that
allow the user greater flexibility in determining what
portions of the device are operating. The power-
managed modes are event driven; that is, some
specific event must occur for the device to enter or
(more particularly) exit these operating modes.
TABLE 3-1:
© 2007 Microchip Technology Inc.
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
®
Mode
devices (where all system clocks are stopped) are
POWER-MANAGED MODES
Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
IDLEN
OSCCON<7,1:0>
POWER-MANAGED MODES
0
0
0
0
1
1
1
SCS1:SCS0
00
00
01
1x
00
01
1x
Clocked
Clocked
Clocked
CPU
Off
Off
Off
Off
Module Clocking
PIC18F2220/2320/4220/4320
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Off
For PIC18F2X20/4X20 devices, the power-managed
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when trig-
gered by an interrupt, a Reset, or a WDT time-out
(PRI_RUN mode is the normal full-power execution
mode; the CPU and peripherals are clocked by the pri-
mary oscillator source). In addition, power-managed
Run modes may also exit to Sleep mode or their
corresponding Idle mode.
3.1
Selecting a power-managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking while the
SC1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
3.1.1
The clock source is selected by setting the SCS bits of
the OSCCON register. Three clock sources are avail-
able for use in power-managed Idle modes: the primary
clock (as configured in Configuration Register 1H), the
secondary clock (Timer1 oscillator) and the internal
oscillator block. The secondary and internal oscillator
block sources are available for the power-managed
modes (PRI_RUN mode is the normal full-power
execution mode; the CPU and peripherals are clocked
by the primary oscillator source).
None – All clocks are disabled
Primary – LP, XT, HS, HSPLL, RC, EC, INTRC
This is the normal full-power execution mode.
Secondary – Timer1 Oscillator
Internal Oscillator Block
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – Timer1 Oscillator
Internal Oscillator Block
Selecting Power-Managed Modes
Available Clock and Oscillator Source
CLOCK SOURCES
(1)
(1)
DS39599G-page 29
(1)
.