PIC18F4320-I/PT Microchip Technology, PIC18F4320-I/PT Datasheet - Page 167

• Manufacturer Part Number: PIC18F4320-I/PT
• Description: IC MCU FLASH 4KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 17-3:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
SMP
2:
3:
4:
This bit is cleared on Reset when SSPEN is cleared or a Start bit has been detected.
This bit is cleared on Reset when SSPEN is cleared or a Stop bit has been detected.
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
ORing this bit with the SSPCON2 bits, SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in
Idle mode.
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled
0 = Slew rate control enabled
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
R/W: Read/Write bit Information (I
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
In Receive mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
R/W-0
CKE
SSPSTAT: MSSP STATUS REGISTER (I
(1)
(2)
W = Writable bit
‘1’ = Bit is set
(3)
(4)
R-0
D/A
PIC18F2220/2320/4220/4320
R-0
P
2
C mode only)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
S
(2)
2
C™ MODE)
R/W
R-0
x = Bit is unknown
R-0
UA
DS39599G-page 165
R-0
BF
bit 0