MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 101

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

of these registers. The CACR and ACRs can only be accessed in supervisor mode using the MOVEC
instruction with an Rc value of 0x002, 0x004 and 0x005, respectively.
4.2.1
The CACR controls the operation of the cache. The CACR provides a set of default memory access
attributes used when a reference address does not map into the spaces defined by the ACRs.
The CACR is a 32-bit, write-only supervisor control register. It is accessed in the CPU address space via
the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in background debug
mode (BDM). Therefore, the register diagram,
entire register is cleared.
Freescale Semiconductor
CENB
30–29
Field
1
2
Reset
Reset
BDM: 0x002 (CACR)
31
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For
more information see
Readable through debug.
W
W
R
R
BDM
0x002
0x004
0x005
CENB
31
15
Cache enable. The memory array of the cache is enabled only if CENB is asserted. This bit, along with the DISI
(disable instruction caching) and DISD (disable data caching) bits, control the cache configuration.
0 Cache disabled
1 Cache enabled
Table 4-3
Reserved, must be cleared.
0
0
0
1
Cache Control Register (CACR)
Cache Control Register (CACR)
Access Control Register 0 (ACR0)
Access Control Register 1 (ACR1)
30
14
0
0
0
0
describes cache configuration.
29
13
0
0
0
0
Chapter 30, “Debug Support.”
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
CPD CFRZ
28
12
0
0
0
Figure 4-2. Cache Control Register (CACR)
Register
27
11
0
0
0
Table 4-2. CACR Field Descriptions
Table 4-1. Cache Memory Map
CEIB DCM DBWE
26
10
0
0
0
25
0
0
0
9
Figure
CINV
Description
24
0
0
8
4-2, is shown as read/write. At system reset, the
DISI
Width
23
(bits)
0
7
0
0
32
32
32
DISD
22
0
0
0
6
Access
DWP EUSP
INVI
W
W
W
21
0
0
5
2
INVD
0x0000_0000
20
Reset Value
See Section
See Section
0
0
4
Access: Supervisor write-only
19
0
0
0
0
3
18
Section/Page
0
0
0
0
2
Debug read/write
4.2.1/4-3
4.2.2/4-6
4.2.2/4-6
17
0
0
0
1
CLNF
Cache
16
0
0
0
0
4-3