MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 407

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

22.3
Table 22-2
22.3.1
The QMR, shown in
such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer size are determined
by this register.
Freescale Semiconductor
1
2
IPSBAR
0x00_034C
Addresses not assigned to a register and undefined register bits are reserved for expansion.
See the register description for special cases. Some bits may be read- or write-only.
Offset:
0x00_0340
0x00_0344
0x00_0348
0x00_0350
0x00_0354
Reset
IPSBAR
Offset
W
R
0x00_0340 (QMR)
MSTR
1
Memory Map/Register Definition
15
Data output (QSPI_DOUT)
Data input (QSPI_DIN)
Serial clock (QSPI_CLK)
Peripheral chip selects (QSPI_CSn)
0
is the QSPI register memory map. Reading reserved locations returns zeros.
QSPI Mode Register (QMR)
QSPI Mode Register (QMR)
QSPI Delay Register (QDLYR)
QSPI Wrap Register (QWR)
QSPI Interrupt Register (QIR)
QSPI Address Register (QAR)
QSPI Data Register (QDR)
Because the QSPI does not operate in slave mode, the master mode enable
bit (QMR[MSTR]) must be set for the QSPI module to operate correctly.
14
0
0
Figure
Signal Name
13
Table 22-1. QSPI Input and Output Signals and Functions
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
22-2, determines the basic operating modes of the QSPI module. Parameters
12
0
BITS
Figure 22-2. QSPI Mode Register (QMR)
Register
11
0
Table 22-2. QSPI Memory Map
10
0
CPOL CPHA
Configurable
N/A
Actively driven
Actively driven
Hi-Z or Actively Driven
0
9
NOTE
1
8
0
7
Width
(bits)
16
16
16
16
16
16
0
6
Serial data output from QSPI
Serial data input to QSPI
Clock output from QSPI
Peripheral selects from QSPI
Access Reset Value
R/W
R/W
R/W
Queued Serial Peripheral Interface (QSPI)
0
5
R/W
R/W
R/W
2
2
2
Function
0
4
BAUD
0x0104
0x0404
0x0000
0x0000
0x0000
0x0000
0
3
Access: User read/write
1
2
Section/Page
22.3.1/22-3
22.3.2/22-5
22.3.3/22-6
22.3.4/22-6
22.3.5/22-7
22.3.6/22-8
0
1
22-3
0
0