MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 62

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

ColdFire Core
The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are
device-specific peripheral interrupt vectors. See
the device-specific interrupt sources.
2-16
All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see
Table
3. The processor saves the current context by creating an exception stack frame on the system stack.
4. The processor calculates the address of the first instruction of the exception handler. By definition,
2-5).
The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to
by the supervisor stack pointer (SSP). As shown in
fixed-length stack frame for all exceptions. The exception type determines whether the program
counter placed in the exception stack frame defines the location of the faulting instruction (fault)
or the address of the next instruction to be executed (next).
the exception vector table is aligned on a 1 MB boundary. This instruction address is generated by
fetching an exception vector from the table located at the address defined in the vector base register.
The index into the exception table is calculated as (4 × vector number). After the exception vector
has been fetched, the vector contents determine the address of the first instruction of the desired
handler. After the instruction fetch for the first opcode of the handler has initiated, exception
processing terminates and normal instruction processing continues in the handler.
Number(s)
Vector
15–23
25–31
6–7
10
11
12
13
14
24
0
1
2
3
4
5
8
9
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 2-5. Exception Vector Assignments
0x03C–0x05C
0x018–0x01C
0x064–0x07C
Offset (Hex)
Vector
0x00C
0x02C
0x000
0x004
0x008
0x010
0x014
0x020
0x024
0x028
0x030
0x034
0x038
0x060
Chapter 10, “Interrupt Controller Modules”
Program
Stacked
Counter
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Next
Next
Next
—
—
—
—
—
—
Figure
Unimplemented line-A opcode
Unimplemented line-F opcode
Initial supervisor stack pointer
Initial program counter
2-16, the processor uses a simplified
Spurious interrupt
Privilege violation
Illegal instruction
Debug interrupt
Divide by zero
Address error
Assignment
Access error
Format error
Reserved
Reserved
Reserved
Reserved
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