MFRC53001T/0FE,112 NXP Semiconductors, MFRC53001T/0FE,112 Datasheet - Page 109

• Manufacturer Part Number: MFRC53001T/0FE,112
• Description: IC MIFARE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC53001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2223-5; 935269692112; MFRC530; MFRC53T0FED

NXP Semiconductors
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. SPI write address . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. EEPROM memory organization diagram . . . . .12
Table 12. Product information field byte allocation . . . . .13
Table 13. Product information field byte description . . . .13
Table 14. Product type identification definition . . . . . . . .13
Table 15. Byte assignment for register initialization at
Table 16. Shipment content of StartUp configuration file .14
Table 17. Byte assignment for register initialization at
Table 18. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .17
Table 19. Associated FIFO buffer registers and flags . . .18
Table 20. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .19
Table 21. Interrupt control registers . . . . . . . . . . . . . . . .19
Table 22. Associated Interrupt request system registers
Table 23. Associated timer unit registers and flags . . . . .24
Table 24. Signal on pins during Hard power-down . . . . .25
Table 25. Pin TX1 configurations . . . . . . . . . . . . . . . . . .28
Table 26. Pin TX2 configurations . . . . . . . . . . . . . . . . . .28
Table 27. TX1 and TX2 source resistance of n-channel
Table 28. Gain factors for the internal amplifier . . . . . . . .33
Table 29. DecoderSource[1:0] values . . . . . . . . . . . . . . .35
Table 30. ModulatorSource[1:0] values . . . . . . . . . . . . . .36
Table 31. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .36
Table 32. Register settings to enable use of the analog
Table 33. MIFARE higher baud rates . . . . . . . . . . . . . . .37
Table 34. Dedicated address bus: assembling the register
Table 35. Multiplexed address bus: assembling the register
Table 36. Behavior and designation of register bits . . . . .40
Table 37. MFRC530 register overview . . . . . . . . . . . . . .41
Table 38. MFRC530 register flags overview . . . . . . . . . .43
MFRC530_33
Product data sheet
PUBLIC
Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Supported microprocessor and EPP interface
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection scheme for detecting the parallel
interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8
start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
driver transistor against GsCfgCW or
GsCfgMod . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
SPI compatibility . . . . . . . . . . . . . . . . . . . . . . .10
SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . .10
SPI read address . . . . . . . . . . . . . . . . . . . . . . . 11
SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 6 July 2010
057433
Table 58. ErrorFlag register bit descriptions . . . . . . . . . . 52
Table 59. CollPos register (address: 0Bh) reset value: 0000
Table 60. CollPos register bit descriptions . . . . . . . . . . . 53
Table 61. TimerValue register (address: 0Ch) reset value:
Table 62. TimerValue register bit descriptions . . . . . . . . 53
Table 63. CRCResultLSB register (address: 0Dh) reset
Table 64. CRCResultLSB register bit descriptions . . . . . 53
Table 65. CRCResultMSB register (address: 0Eh) reset
Table 66. CRCResultMSB register bit descriptions . . . . 54
Table 67. BitFraming register (address: 0Fh) reset value:
Table 68. BitFraming register bit descriptions . . . . . . . . . 54
Table 69. TxControl register (address: 11h) reset value:
Table 39. Page register (address: 00h, 08h, 10h, 18h, 20h,
Table 40. Page register bit descriptions . . . . . . . . . . . . . 46
Table 41. Command register (address: 01h) reset value:
Table 42. Command register bit descriptions . . . . . . . . . 46
Table 43. FIFOData register (address: 02h) reset value:
Table 44. FIFOData register bit descriptions . . . . . . . . . 47
Table 45. PrimaryStatus register (address: 03h) reset value:
Table 46. PrimaryStatus register bit descriptions . . . . . . 47
Table 47. FIFOLength register (address: 04h) reset value:
Table 48. FIFOLength bit descriptions . . . . . . . . . . . . . . 48
Table 49. SecondaryStatus register (address: 05h) reset
Table 50. SecondaryStatus register bit descriptions . . . . 49
Table 51. InterruptEn register (address: 06h) reset value:
Table 52. InterruptEn register bit descriptions . . . . . . . . 49
Table 53. InterruptRq register (address: 07h) reset value:
Table 54. InterruptRq register bit descriptions . . . . . . . . 50
Table 55. Control register (address: 09h) reset value: 0000
Table 56. Control register bit descriptions . . . . . . . . . . . 51
Table 57. ErrorFlag register (address: 0Ah) reset value:
28h, 30h, 38h) reset value: 1000 0000b, 80h bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
x000 0000b, x0h bit allocation . . . . . . . . . . . . 46
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 47
0000 0101b, 05h bit allocation . . . . . . . . . . . . 47
0000 0000b, 00h bit allocation . . . . . . . . . . . . 48
value: 01100 000b, 60h bit allocation . . . . . . . 49
0000 0000b, 00h bit allocation . . . . . . . . . . . . 49
0000 0000b, 00h bit allocation . . . . . . . . . . . . 50
0000b, 00h bit allocation . . . . . . . . . . . . . . . . . 51
0100 0000b, 40h bit allocation . . . . . . . . . . . . 52
0000b, 00h bit allocation . . . . . . . . . . . . . . . . . 53
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 53
value: xxxx xxxxb, xxh bit allocation . . . . . . . . 53
value: xxxx xxxxb, xxh bit allocation . . . . . . . . 54
0000 0000b, 00h bit allocation . . . . . . . . . . . . 54
0101 1000b, 58h bit allocation . . . . . . . . . . . . 55
ISO/IEC 14443 A Reader IC
MFRC530
© NXP B.V. 2010. All rights reserved.
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