MFRC53001T/0FE,112 NXP Semiconductors, MFRC53001T/0FE,112 Datasheet - Page 47

• Manufacturer Part Number: MFRC53001T/0FE,112
• Description: IC MIFARE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC53001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2223-5; 935269692112; MFRC530; MFRC53T0FED

NXP Semiconductors
MFRC530_33
Product data sheet
PUBLIC
10.5.1.3 FIFOData register
10.5.1.4 PrimaryStatus register
Input and output of the 64 byte FIFO buffer.
Table 43.
Table 44.
Bits relating to receiver, transmitter and FIFO buffer status flags.
Table 45.
Table 46.
Bit
Symbol
Access
Bit
7 to 0
Bit
Symbol
Access
Bit
7
6 to 4 ModemState[2:0]
3
Symbol
0
IRq
Symbol
FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. The FIFO
FIFOData register (address: 02h) reset value: xxxx xxxxb, xxh bit allocation
FIFOData register bit descriptions
PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation
PrimaryStatus register bit descriptions
All information provided in this document is subject to legal disclaimers.
R
7
0
7
Rev. 3.3 — 6 July 2010
Description
buffer acts as a parallel in to parallel out converter for all data streams.
Value Status
-
000
001
010
011
100
101
110
111
-
6
ModemState[2:0]
6
057433
Idle
TxSOF
TxData
TxEOF
GoToRx1
GoToRx2
PrepareRx
AwaitingRx
Receiving
R
5
5
4
Description
reserved
shows the state of the transmitter and receiver
state machines:
shows any interrupt source requesting attention
based on the InterruptEn register flag settings
neither the transmitter or receiver are operating;
neither of them are started or have input data
transmit start of frame pattern
transmit data from the FIFO buffer (or
redundancy CRC check bits)
transmit End Of Frame (EOF) pattern
intermediate state 1; receiver starts
intermediate state 2; receiver finishes
waiting until the RxWait register time period
expires
receiver activated; waiting for an input signal on
pin RX
receiving data
FIFOData[7:0]
4
IRq
R
3
D
3
Err
R
2
ISO/IEC 14443 A Reader IC
2
MFRC530
HiAlert
© NXP B.V. 2010. All rights reserved.
R
1
1
LoAlert
47 of 115
R
0
0