MFRC53001T/0FE,112 NXP Semiconductors, MFRC53001T/0FE,112 Datasheet - Page 52

IC MIFARE HS READER 32-SOIC

MFRC53001T/0FE,112

Manufacturer Part Number
MFRC53001T/0FE,112
Description
IC MIFARE HS READER 32-SOIC
Manufacturer
NXP Semiconductors
Series
MIFARE®r
Datasheets

Specifications of MFRC53001T/0FE,112

Rf Type
Read Only
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B, ISO15693
Package / Case
32-SOIC (0.300", 7.50mm Width)
Product
RFID Readers
Operating Temperature Range
- 25 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2223-5
935269692112
MFRC530
MFRC53T0FED

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MFRC53001T/0FE,112
Manufacturer:
MICROCHIP
Quantity:
12 000
NXP Semiconductors
MFRC530_33
Product data sheet
PUBLIC
10.5.2.3 ErrorFlag register
Error flags show the error status of the last executed command.
Table 57.
Table 58.
Bit
Symbol
Access
Bit
7
6
5
4
3
2
1
0
Symbol
0
KeyErr
AccessErr
FIFOOvfl
CRCErr
FramingErr
ParityErr
CollErr
ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation
ErrorFlag register bit descriptions
R
7
0
All information provided in this document is subject to legal disclaimers.
Value
-
1
0
1
0
1
1
0
1
0
1
0
1
0
KeyErr AccessErr
R
6
Rev. 3.3 — 6 July 2010
Description
reserved
set when the LoadKeyE2 or LoadKey command recognize that the
input data is not encoded based on the key format definition
set when the LoadKeyE2 or the LoadKey command starts
set when the access rights to the EEPROM are violated
set when an EEPROM related command starts
set when the microprocessor or MFRC530 internal state machine
(e.g. receiver) tries to write data to the FIFO buffer when it is full
set when RxCRCEn is set and the CRC fails
automatically set during the PrepareRx state in the receiver start
phase
set when the SOF is incorrect
automatically set during the PrepareRx state in the receiver start
phase
set when the parity check fails
automatically set during the PrepareRx state in the receiver start
phase
set when a bit-collision is detected
automatically set during the PrepareRx state in the receiver start
phase
057433
R
5
FIFOOvfl
R
4
CRCErr FramingErr
R
3
ISO/IEC 14443 A Reader IC
R
2
MFRC530
© NXP B.V. 2010. All rights reserved.
ParityErr
R
1
CollErr
52 of 115
R
0

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