MFRC53001T/0FE,112 NXP Semiconductors, MFRC53001T/0FE,112 Datasheet - Page 19

• Manufacturer Part Number: MFRC53001T/0FE,112
• Description: IC MIFARE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC53001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2223-5; 935269692112; MFRC530; MFRC53T0FED

NXP Semiconductors
Table 21.
MFRC530_33
Product data sheet
PUBLIC
Register
InterruptEn
InterruptRq
Interrupt control registers
9.4.2.1 Controlling interrupts and getting their status
9.4.2.2 Accessing the interrupt registers
9.4.2 Interrupt request handling
Bit 7
SetIEn
SetIRq
When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page
logic 1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3
Table 20.
The MFRC530 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
If an interrupt request flag is set to logic 1 (showing that an interrupt request is pending)
and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is
set to logic 1. Different interrupt sources can activate simultaneously and because of this,
all interrupt request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ.
The interrupt request bits are automatically set by the MFRC530’s internal state
machines. In addition, the microprocessor can also set or clear the interrupt request bits
as required.
A special implementation of the InterruptRq and InterruptEn registers enables changing
an individual bit status without influencing any other bits. If an interrupt register is set to
logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. Vice
versa, if a specific interrupt flag is cleared, zero must be written to the SetIxx and the
interrupt register address must be set to logic 1 at the same time.
If a content bit is not changed during the setting or clearing phase, zero must be written to
the specific bit location.
Interrupt flag
TimerIRq
TxIRq
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
Bit 6
reserved
reserved
Interrupt sources
and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to logic 1.
All information provided in this document is subject to legal disclaimers.
receiver
Interrupt source
timer unit
transmitter
CRC coprocessor
EEPROM
Command register
FIFO buffer
FIFO buffer
TimerIRq
Bit 5
TimerIEn
17) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to
Rev. 3.3 — 6 July 2010
057433
Bit 4
TxIEn
TxIRq
RxIRq
Bit 3
RxIEn
Trigger action
timer counts from 1 to 0
a data stream, transmitted to the card, ends
all data from the FIFO buffer has been processed
all data from the FIFO buffer has been
programmed
a data stream, received from the card, ends
command execution finishes
FIFO buffer is full
FIFO buffer is empty
Bit 2
IdleIEn
IdleIRq
ISO/IEC 14443 A Reader IC
Bit 1
HiAlertIEn
HiAlertIRq
MFRC530
© NXP B.V. 2010. All rights reserved.
Bit 0
LoAlertIEn
LoAlertIRq
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