WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 27

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

5.2.3.2
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Figure 3. Management Interface Read Frame Structure
Figure 4. Management Interface Write Frame Structure
5.2.3.1.2 MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is
shown in
MDIO Interface timing is given in
Hardware Control Interface
The LXT972M Transceiver provides a Hardware Control Interface for applications where the
MDIO is not desired. The Hardware Control Interface uses the hardware configuration pins to set
device configuration. For details, see
page
MDIO
(Read)
(Write)
MDC
MDIO
MDC
High Z
33.
Idle
Preamble
Figure 3
32 "1"s
Preamble
32 "1"s
0
0
ST
and
ST
1
1
Figure 4
1
0
Op Code
Op Code
1
0
Intel
(Read and Write).
Write
A4
A4
Chapter 7.0, “Electrical Specifications”.
®
PHY Address
PHY Address
Section 5.4.4, “Hardware Configuration Settings” on
LXT972M Single-Port 10/100 Mbps PHY Transceiver
A3
A3
A0
A0
Write
R4
R4
Register Address
Register Address
R3
R3
R0
R0
1
Z
Around
Around
Turn
Turn
0
0
D15
D15
D15
D14
D14
Data
Read
D14
Data
D1
D1
D1
D0
D0
Idle
B3490-01
Idle
B3489-01
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