WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 32

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WJLXT972MLC.A4 S L7U9

Manufacturer Part Number
WJLXT972MLC.A4 S L7U9
Description
Manufacturer
Intel
Datasheet

Specifications of WJLXT972MLC.A4 S L7U9

Lead Free Status / RoHS Status
Compliant
Intel
32
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
For pin settings used during a hardware reset, see
Settings”. During a hardware reset, configuration settings for auto-negotiation and speed are read
in from pins, and register information is unavailable for 1 ms after de-assertion of the reset.
During a software reset, bit settings in
Address 4, Hex 4” on page 79
pins. Instead, the bit settings revert to the values that were read in during the last hardware
reset. Therefore, any changes to pin values made since the last hardware reset are not detected
during a software reset.
During a software reset, registers are available for reading. To see when the LXT972M
Transceiver has completed reset, the reset bit can be polled (that is, Register bit 0.15 = 0).
are not re-read from the LXT972M Transceiver configuration
Table 45, “Auto-Negotiation Advertisement Register -
Section 5.4.4, “Hardware Configuration
Document Number: 302875-005
Revision Date: 27-Oct-2005
Datasheet

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