WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 56

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Intel
5.10.4
5.10.5
56
Table 17. BSR Mode of Operation
Table 18. Device ID Register for Intel
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage.
Device ID Register
Table 18
characters, see the specification update for the LXT972M Transceiver.
1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC ID is FE
Mode
Bits 31:28
Version
(1111 1110), which becomes 111 1110.
1
2
3
4
XXXX
lists the bits for the Device ID register. For the current version of the JEDEC continuation
Part ID (Hex)
System Function
Bits 27:12
Description
03CB
Capture
Update
Shift
®
LXT972M Transceiver
JEDEC Continuation Characters
Table 17
Bits 11:8
0000
lists the four BSR modes of operation.
JEDEC ID
Document Number: 302875-005
111 1110
Bits 7:1
Revision Date: 27-Oct-2005
1
Datasheet
Reserved
Bit 0
1