WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 39

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

5.6.4
5.6.5
5.6.6
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Table 14. Carrier Sense, Loopback, and Collision Conditions
Carrier Sense
Carrier Sense (CRS) is an asynchronous output.
Table 14
signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
Error Signals
When the LXT972M Transceiver is in 100 Mbps mode and receives an invalid symbol from the
network, it asserts RX_ER and drives “0101” on the RXD pins.
The TX_ER function that forces ‘H’ symbols out on the TPOP/TPON twisted pair is not
implemented in the LXT972M Transceiver.
Collision
The LXT972M Transceiver asserts its collision signal asynchronously to any clock whenever the
line state is half-duplex and the transmitter and receiver are active at the same time.
summarizes the conditions for assertion of carrier sense, data loopback, and collision signals.
100
Mbps
10
Mbps
Speed
1. Test Loopback is enabled when Register bit 0.14 = 1.
2. For descriptions of Test Loopback and Operational Loopback, see
•
•
CRS is always generated when the LXT972M Transceiver receives a packet from the line.
CRS is also generated when the LXT972M Transceiver is in half-duplex mode when a packet
is transmitted.
summarizes the conditions for assertion of carrier sense, data loopback, and collision
Full-Duplex
Half-Duplex
Full-Duplex
Half-Duplex,
Register bit 16.8 = 0
Half-Duplex,
Register bit 16.8 = 1
Duplex Condition
Receive Only
Transmit or Receive
Receive Only
Transmit or Receive
Transmit or Receive
Intel
Carrier Sense
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Loop-
back
Test
Yes
Yes
Yes
No
No
1, 2
Section 5.6.7, “Loopback” on page
Operational
back
Loop-
Yes
No
No
No
No
1, 2
None
Transmit and Receive
None
Transmit and Receive
Transmit and Receive
Collision
Table 14
40.
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