WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 41

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

5.6.7.2
5.7
5.7.1
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Figure 11. 100BASE-X Frame Format
Internal Digital Loopback (Test Loopback)
A test loopback function is provided for diagnostic testing of the LXT972M Transceiver. During
test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is
internally looped back by the LXT972M Transceiver and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by
setting the following register bits:
100 Mbps Operation
100BASE-X Network Operations
During 100BASE-X operation, the LXT972M Transceiver transmits and receives 5-bit symbols
across the network link.
Figure 11
not actively transmitting data, the LXT972M Transceiver sends out Idle symbols on the line.
As
LXT972M Transceiver detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT972M Transceiver transmits the End-of-Stream Delimiter (ESD,
symbols T and R) and then returns to transmitting Idle symbols.
For details on the symbols used, see 4B/5B coding listed in
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
•
•
•
P0
Figure 11
Register bit 0.14 = 1 (Setting to enable loopback mode)
Register bit 0.8 = 1 (Setting for full-duplex mode)
Register bit 0.12 = 0. (Disable auto-negotiation.)
64-Bit Preamble
P1
(8 Octets)
shows the structure of a standard frame packet in 100BASE-X mode. When the MAC is
P6
shows, the MAC starts each transmission with a preamble pattern. As soon as the
Delimiter (SFD)
Start-of-Frame
SFD
DA
Address (6 Octets each)
Destination and Source
DA
Intel
SA
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
SA
Packet Length
L1
(2 Octets)
L2
(Pad to minimum packet size)
D0
Data Field
D1
Table 15, “4B/5B Coding” on page
Dn
Frame Check Field
(4 Octets)
CRC
End-of-Stream Delimiter (ESD)
/T/R/ code-groups
Replaced by
B3466-01
InterFrame Gap / Idle Code
I0
(> 12 Octets)
IFG
46.
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