WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 76

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Intel
76
Table 41. Control Register - Address 0, Hex 0
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Table 41
1. R/W = Read/Write
2. Some bits have their default values determined at reset by hardware configuration pins. For default details
0.5:0
0.15
0.14
0.13
0.12
0.10
0.11
Bit
0.9
0.8
0.7
0.6
SC = Self Clearing
for these bits, see
lists control register bits.
Reset
Loopback
Speed Selection
Auto-Negotiation
Enable
Power-Down
Isolate
Restart Auto-
Negotiation
Duplex Mode
Collision Test
Speed Selection
Reserved
Name
Section 5.4.4, “Hardware Configuration
0 = Normal operation
1 = PHY reset
0 = Disable loopback mode
1 = Enable loopback mode
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
0 = Normal operation
1 = Power-down
0 = Normal operation
1 = Electrically isolate PHY from MII
0 = Normal operation
1 = Restart auto-negotiation process
0 = Half-duplex
1 = Full-duplex
0 = Disable COL signal test
1 = Enable COL signal test
Write as ‘0’. Ignore on Read.
X - 0.6
0.6
0
0
1
1
0
0
1
1
0.13
0.13
0
1
0
1
0
1
0
1
10 Mbps
100 Mbps
1000 Mbps (not supported)
Reserved
10 Mbps
100 Mbps
1000 Mbps (not supported)
Reserved
Description
Speed Selected
Speed Selected
Settings”.
Document Number: 302875-005
Revision Date: 27-Oct-2005
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SC
SC
1
Datasheet
Default
Note 2
Note 2
Note 2
00000
0
0
0
0
0
0
0