WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 67

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WJLXT972MLC.A4 S L7U9

Manufacturer Part Number
WJLXT972MLC.A4 S L7U9
Description
Manufacturer
Intel
Datasheet

Specifications of WJLXT972MLC.A4 S L7U9

Lead Free Status / RoHS Status
Compliant
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Figure 24. Intel
Table 32. Intel
RXD, RX_DV. Setup to RX_CLK High.
RXD, RX_DV, RX_ER Hold from
RX_CLK High
TPIP/N in to RXD out (Rx latency)
CRS asserted to RXD, RX_DV,
RX_ER asserted
RXD, RX_DV, RX_ER de-asserted to
CRS de-asserted
TPI in to CRS asserted
TPI quiet to CRS de-asserted
TPI in to COL asserted
TPI quiet to COL de-asserted
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
testing.
rate. 10BASE-T bit time = 10
RX_CLK
®
RX_DV,
®
RX_ER
LXT972M Transceiver 10BASE-T Receive Timing
RXD,
LXT972M Transceiver 10BASE-T Receive Timing
CRS
COL
TPI
Parameter
t
6
-7
t
8
Intel
s or 100 ns.
t
3
®
t
LXT972M Single-Port 10/100 Mbps PHY Transceiver
4
Sym
t1
t2
t3
t4
t5
t6
t7
t8
t9
Min
4.2
0.3
10
10
2
5
6
1
5
t
1
Typ
t
2
1
Max
6.6
0.5
32
28
10
31
10
Units
BT
BT
BT
BT
BT
BT
BT
ns
ns
t
t
7
9
2
t
B3457-01
Test Conditions
5
67

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