PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 333

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

21.4.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware if the
TRIS bits are set.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I
set, or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 21-18:
 2009-2011 Microchip Technology Inc.
SDAx
SCLx
Assert a Start condition on SDAx and SCLx.
Assert a Repeated Start condition on SDAx and
SCLx.
Write to the SSPxBUF register, initiating
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
MASTER MODE
2
C bus operations based on Start and
2
C bus may be taken when the P bit is
2
C port to receive data.
MSSP BLOCK DIAGRAM (I
SDAx In
SCLx In
Bus Collision
Read
MSb
Write Collision Detect
Start bit, Stop bit,
End of XMIT/RCV
State Counter for
Clock Arbitration
Acknowledge
Start bit Detect
Stop bit Detect
SSPxBUF
SSPxSR
Generate
2
C™ MASTER MODE)
LSb
PIC18F87K90 FAMILY
Write
The following events will cause the MSSPx Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmitted
• Repeated Start
Clock
Internal
Data Bus
Shift
Note:
Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1);
Set SSPxIF, BCLxIF;
Reset ACKSTAT, PEN (SSPxCON2)
The MSSPx module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
2
C Master mode, does not allow queueing
SSPxADD<6:0>
SSPM<3:0>
Generator
Baud
Rate
DS39957D-page 333