PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 65

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

4.6
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see
“Sleep Mode”
4.6.1
Any of the available interrupt sources can cause the
device to exit from an Idle or Sleep mode to a Run
mode. To enable this functionality, an interrupt source
must be enabled by setting its enable bit in one of the
INTCONx or PIEx registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the GIE/
GIEH bit (INTCON<7>) is set. Otherwise, code execu-
tion continues or resumes without branching (see
Section 10.0
4.6.2
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed
Modes”
is executing code (all Run modes), the time-out will
result in a WDT Reset (see
Timer
Executing a SLEEP or CLRWDT instruction clears the
WDT timer and postscaler, loses the currently selected
clock source (if the Fail-Safe Clock Monitor is enabled)
and modifies the IRCF bits in the OSCCON register (if
the internal oscillator block is the device clock source).
 2009-2011 Microchip Technology Inc.
(WDT)”).
and
Exiting Idle and Sleep Modes
EXIT BY INTERRUPT
EXIT BY WDT TIME-OUT
Section 4.2 “Run
Section 4.3 “Sleep
“Interrupts”).
and
mode
Section 4.4 “Idle
(see
Section 28.2 “Watchdog
Modes”,
Mode”). If the device
Section 4.2
Modes”).
Section 4.3
“Run
PIC18F87K90 FAMILY
4.6.3
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the HFIOFS/MFIOFS bits are set
instead.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up, and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 28.4 “Two-Speed
Clock Monitor (see
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution is
clocked by the INTOSC multiplexer, driven by the inter-
nal oscillator block. Execution is clocked by the internal
oscillator block until either the primary clock becomes
ready or a power-managed mode is entered before the
primary clock becomes ready; the primary clock is then
shut down.
4.6.4
Certain exits from power-managed modes do not
invoke the OST at all. The two cases are:
• When in PRI_IDLE mode, where the primary
• When the primary clock source is not any of the
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
clock source is not stopped
LP, XT, HS or HSPLL modes
, following the wake event, is still required when
EXIT BY RESET
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Table
4-4.
Section 28.5 “Fail-Safe Clock
Start-up”) or Fail-Safe
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