PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 456

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
TABLE 29-2:
DS39957D-page 456
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
DATA MEMORY  PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Note 1:
Mnemonic,
Operands
2:
3:
4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0 ), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘ 1 ’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘ 0 ’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1 ), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP .
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
k
k
k
f, k
k
k
k
k
k
k
PIC18F87K90 FAMILY INSTRUCTION SET (CONTINUED)
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG
Move literal (12-bit) 2nd word
Move Literal to BSR<3:0>
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
Exclusive OR Literal with WREG
Table Read
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
to FSR(f)
Description
1st word
1
1
1
2
1
1
1
2
1
1
2
2
Cycles
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
MSb
16-Bit Instruction Word
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
0000
0000
0000
0000
0000
0000
0000
0000
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
0000
0000
0000
0000
0000
0000
0000
0000
 2009-2011 Microchip Technology Inc.
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
1000
1001
1010
1011
1100
1101
1110
1111
LSb
C, DC, Z, OV, N
Z, N
Z, N
None
None
None
None
None
C, DC, Z, OV, N
Z, N
None
None
None
None
None
None
None
None
Affected
Status
Notes