LSISAS1064 LSI, LSISAS1064 Datasheet
LSISAS1064
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... TECHNICAL MANUAL LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller Version 3.2 ® DB14-000274-05 ...
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... C standard Specification as defined by Philips. Document DB14-000274-05, Version 3.2 (October 2005) This document describes the LSI Logic Corporation’s LSISAS1064 Serial Attached SCSI Controller and will remain the official reference source for all revisions/releases of this product until rescinded by an update. ...
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... Preface This book is the primary reference and technical manual for the LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller. It contains a complete functional description for the LSISAS1064, as well as the physical and electrical specifications for the LSISAS1064. Audience This document assumes that you are familiar with microprocessors and related support devices. The people who benefi ...
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... Appendix A, Register LSISAS1064. Related Publications LSI Logic Documents Fusion-MPT DB15-000186-02 LSI Logic World Wide Web Home Page www.lsilogic.com ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 InterNational Committee on Information Technology Standards (INCITIS) T10 Technical Committee http://www.t10.org Global Engineering Documents ...
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... Preliminary Version 2.0 11/2004 Updated PCI and Power Management specification revision numbers. Advance Version 0.3 1/2004 Advance Version 0.2 12/2003 Initial release of document. Preface Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Remarks Updated external memory diagrams. Removed references to Serial EEPROM not supported with this device. 2 Added I C and SFF-8485 specifi ...
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... Preface Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Fusion-MPT Architecture Overview 2.3 PCI Functional Description 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ® Transceivers SAS Features SATA Features PCI Performance Integration Usability Flexibility ...
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... DC Characteristics 5.2 AC Characteristics 5.3 External Memory Timing Diagrams viii Contents Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Memory Requirements Flash ROM Controller NVSRAM Controller PCI System Signals PCI Address and Data Signals PCI Interface Control Signals PCI Arbitration Signals ...
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... Pinout 5.5 Package Drawings Appendix A Register Summary Index Customer Feedback Contents Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. 5-12 5-20 ix ...
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... Contents Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Narrow and Wide Links 2.4 SSP, STP, and SMP Protocol Usage 2.5 Flash ROM Block Diagram 2.6 NVSRAM Block Diagram 2.7 ZCR Circuit Diagram for the LSISAS1064 3.1 LSISAS1064 Functional Signal Grouping 5.1 External Clock 5.2 Reset Input 5.3 Interrupt Output 5 ...
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... Contents Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Test and JTAG Signals 3.14 Power and Ground Signals 3.15 Power-On Sense Pin Definitions 3.16 Pull-Up and Pull-Down Conditions 4.1 LSISAS1064 PCI Configuration Space Address Map 4.2 Multiple Message Enable Field Bit Encoding 4.3 BIR Field Definitions 4.4 Maximum Outstanding Split Transactions 4.5 Maximum Memory Read Count 4 ...
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... Listing by Signal Name 5.32 Listing by Pin Number A.1 LSISAS1064 PCI Configuration Space Registers A.2 LSISAS1064 PCI I/O Space Registers A.3 LSISAS1064 PCI Memory [0] Space Registers xiv Contents Version 3.1 Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. 5-3 5-3 5-4 ...
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... PCI or PCI-X high-performance SAS/SATA phys and a 64-bit, 133 MHz PCI-X bus master DMA core. Each of the four phys on the LSISAS1064 is capable of 3.0 Gbit/s and 1.5 Gbit/s SAS link rates, and 3.0 Gbit/s and 1.5 Gbit/s SATA link rates. The LSISAS1064 supports the SAS protocol as described in the Serial Attached SCSI Standard, version 1 ...
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... LSI Logic produces the LSISAS1064 using the Gflx Each port on the LSISAS1064 supports SAS and SATA devices using the SAS Serial SCSI Protocol (SSP), Serial Management Protocol (SMP), Serial Tunneling Protocol (STP), and SATA. The SSP protocol enables communication with other SAS devices ...
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... PCI/PCI-X Interface LSISAS1064 LSISASx12 SAS/SATA SAS/SATA Drives Drives The LSISAS1064 employs an ARM926 processor to meet the data transfer flexibility requirements of the host interface PCI-X specifications. General Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. 32-bit Memory Address/Data LSISAS1064 ...
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... PSBRAM devices. Most configurations use a Flash ROM to store firmware, configuration information, and persistent data information. The LSISAS1064 supports the Integrated RAID solution, which is a highly integrated, low cost RAID implementation designed for systems requiring redundancy and high availability, but not needing a full- featured RAID implementation ...
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... ATA firmware. The LSISAS1064 can function as an SSP initiator, an SSP target, an SMP initiator, an STP initiator SATA initiator. The LSISAS1064 uses SSP to communicate with other SAS devices, and uses SMP to communicate topology management information with other SAS devices. ...
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... PCI-X also reduces host processor overhead by providing a wide range of error recovery implementations. The LSISAS1064 supports 133 MHz, 64-bit PCI-X bus and is backwards compatible with previous versions of the PCI/PCI-X specification. Per the PCI-X addendum, the LSISAS1064 includes ...
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... Each PCI-X transaction contains a transaction sequence identifier (Tag), the identity of the initiator, and the number of bytes in the sequence. The LSISAS1064 clocks PCI-X data directly into and out of registers, which creates a more efficient data path. The LSISAS1064 increases bus efficiency since it does not insert wait states after the initial data phase when acting as a PCI-X target and never inserts wait states when acting as a PCI-X initiator ...
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... Eliminates the Master-Slave construction used in parallel ATA Allows addressing of multiple SATA targets through an expander Allows multiple initiators to address a single target (in a fail-over configuration) through an expander 1.6.3 PCI Performance The LSISAS1064 supports these PCI features: 133 MHz, 64-bit PCI/PCI-X interface that: – – – 1-8 Introduction Copyright © ...
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... Integration These features make the LSISAS1064 easy to integrate: Supports backwards compatibility with previous revisions of the PCI specification, with the exception that the LSISAS1064 does not support 5 V PCI Summary of LSISAS1064 Features Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Leverages compatible connectors for SAS and SATA connections Allows grouping phys to form a wide port Allows programming of the World Wide Name 1.6.7 Reliability These features enhance the reliability of the LSISAS1064: Uses proven GigaBlaze transceivers 1-10 Introduction Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Has a high proportion of power and ground pins Integrated RAID solution provides Integrated Mirroring technology and Integrated Striping technology Supports Zero Channel RAID 1.6.8 Testability These features enhance the testability of the LSISAS1064: Offers JTAG boundary scan Provides a UART interface for debugging Offers ARM Multi-ICE processor Offers I Summary of LSISAS1064 Features Copyright © ...
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... Introduction Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Section 2.6, “Zero Channel RAID” Section 2.7, “Universal Asynchronous Receiver/Transmitter (UART)” Section 2.8, “Multi-ICE Test Interface” The LSISAS1064 is a four port 3.0 Gbit/s SAS controller that is compliant with the Fusion-MPT architecture, provides a PCI-X interface, and supports Integrated RAID solution. The LSISAS1064 supports version 3.0 of the PCI Local Bus Specifi ...
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... Block Diagram Description The LSISAS1064 consists of two major modules and a context RAM. The two major modules are the host interface module and the Quad Port module. The modules consist of the following components: Host Interface Module – – – – – ...
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... Figure 2.1 LSISAS1064 Controller Block Diagram Host Interface PCI-X 133MHz TimerConfig PCI/PCI-X Interface DMA Arbiter System Interface IOP ICE I/F AHB Arbiter (ARM926 Processor) IRQ Controller GPIO/LED TimerConfig XMEM Bus External Memory UART UART 2.1.1 Host Interface Module Description The host interface module provides an interface between the host driver and the Quad Port ...
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... The LSISAS1064 provides a PCI-X interface that supports 64-bit, 133 MHz PCI-X bus. The LSISAS1064 PCI interface is backward compatible with previous implementations of the PCI specification, with the exception that the LSISAS1064 does not support 5 V PCI. For more information on the PCI interface, refer to Description.” ...
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... Timer and Configuration This block supports the LSISAS1064 LED and GPIO interfaces. There are a total of nine LED signals on the LSISAS1064. Each of the four phys has an LED signal to indicate activity on the link and an LED signal to indicate an error on the link. The GPIO interface contains four independent GPIO signals. The LED signals can also be confi ...
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... Transport Module The transport modules transmit frames to and from the port layer and implement the STP, SSP, and SMP protocols. There are four instances of the transport module, one for each SAS/SATA phy on the LSISAS1064. 2.1.2.2 Queue Manager The queue manager is responsible for managing various queue structures that support the SSP, SMP, and STP protocols ...
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... There are two, 32-bit message queues: the request message queue and the reply message queue. The host uses the request queue to request an action by the LSISAS1064, and the LSISAS1064 uses the reply queue to return status information to the host. The request message Fusion-MPT Architecture Overview Copyright © ...
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... Version 3.0 and the PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0. The LSISAS1064 supports a 133 MHz, 64-bit PCI-X bus. The LSISAS1064 provides support for 64-bit addressing with Dual Address Cycle (DAC). The LSISAS1064 does not support 5 V PCI signaling. 2-8 Functional Description Copyright © ...
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... IDSEL is not asserted. Bits AD[10:8] address the PCI Function Configuration Space (AD[10:8] = 0b000). The LSISAS1064 does not respond to any other encodings of AD[10:8]. Bits AD[7:2] select one of the 64 Dword registers in the device’s PCI Configuration Space. Bits AD[1:0] determine if the confi ...
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... The LSISAS1064 contains two PCI memory spaces: PCI Memory Space [0] and PCI Memory Space [1]. PCI Memory Space [0] supports normal memory accesses while PCI Memory Space [1] supports diagnostic memory accesses. The LSISAS1064 requires 64 Kbytes of memory space. The PCI specification defines memory space as a contiguous 64-bit memory address that all system resources share ...
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... When acting as a slave in the PCI mode, the LSISAS1064 supports this command as the PCI Memory Read command. 3. When acting as a slave in the PCI mode, the LSISAS1064 supports this command as the PCI Memory Write command. The following sections describe how the LSISAS1064 implements these commands ...
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... The Memory Read Dword command reads single Dword of data from an agent mapped in the memory address space and can only be initiated as a 32-bit transaction. The target can perform an anticipatory read if such a read produces no side effects. The LSISAS1064 supports this command when operating in the PCI-X bus mode. 2.3.2.7 ...
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... Burst Size Selection – The Read Multiple command reads multiple cache lines of data during a single bus ownership. The number of cache lines the LSISAS1064 reads is a multiple of the cache line size, which Revision 3.0 of the PCI specification provides. The LSISAS1064 selects the largest multiple of the cache line size based on the amount of data to transfer ...
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... Memory Read Line Command This command is identical to the Memory Read command except it additionally indicates that the master intends to fetch a complete cache line. The LSISAS1064 supports this command when operating in the PCI mode. 2.3.2.16 Memory Read Block Command The LSISAS1064 uses this command to read from memory. The LSISAS1064 supports this command when operating in the PCI-X mode ...
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... The PCI Local Bus specification states that the transfer size must be a multiple of the cache line size. The LSISAS1064 selects the largest multiple of the cache line size based on the transfer size. When the DMA buffer contains less data than the value ...
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... PCI Interrupts The LSISAS1064 signals an interrupt to the host processor either using PCI interrupt pins (INTA/ and ALT_INTA/), or Message Signaled Interrupts (MSI and MSI-X). The Interrupt Request Routing Mode bits in the Host Interrupt Mask either the INTA/ and/or the ALT_INTA/ pin. ...
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... A narrow port contains a single phy, while a wide port contains multiple phys. The LSISAS1064 supports wide ports that contain up to four phys. Any of the LSISAS1064 ports can combine to form a wide port. Since each phy within a wide port can transmit data at 3 ...
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... Narrow Link Containing One Phy in each Port b. Wide Link Containing Three Phys in each Port Wide Port Each phy on the LSISAS1064 can function as an SSP Initiator, an SSP target, an SMP initiator, an STP initiator SATA Initiator. A phy can function in only one role during a connection, but function in different roles during different connections ...
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... AHB bus and an external 32-bit memory interface. This interface is for accessing external Flash ROM and NVSRAM devices. Because the LSISAS1064 uses a 32-bit multiplexed address/data bus, designs using the LSISAS1064 do not require latches or CPLD devices to construct memory addresses. 2.5.1 ...
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... The LSISAS1064 Flash ROM interface provides access to nonvolatile code and parameter storage for both the embedded ARM core and the host system. An 8-bit wide Flash ROM is optional if the LSISAS1064 is not the boot device, and a suitable driver exists to initialize the LSISAS1064 and download its code. The Flash ROM interface: ...
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... Intel/Sharp extended command set and/or AMD/Fujitsu extended command set programming algorithms The Fusion-MPT firmware for the LSISAS1064 supports all CFI Flash parts and a limited set of non-CFI Flash parts. Contact the LSI Logic or OEM representative for a current list of supported non-CFI Flash parts. ...
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... NVSRAM and returns the resulting 32-bit Dword for each AHB Dword read request Byte lane 3 of the LSISAS1064 external memory bus (MAD[31:24]) connects to the 8-bit data bus of the NVSRAM. BWE[2]/ provides the write enable signal for the NVSRAM. The MOE[0]/ signal enables the attached NVSRAM to drive data. NVSRAM confi ...
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... LSISAS1064 responds to PCI configuration cycles when the ALT_GNT/ signal is asserted. Connect the ALT_GNT/ pin on the LSISAS1064 to the PCI GNT/ signal of the external I/O processor. This allows the I/O processor to perform PCI configuration cycles to the LSISAS1064 when the I/O processor is granted the PCI bus. This confi ...
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... Int B/ Int C/ Int D/ AD21 AD19 Note: To maintain proper interrupt mapping, select the address line for use as IDSEL on the LSISAS1064 address lines above IDSEL on ZCR slot. 2.7 Universal Asynchronous Receiver/Transmitter (UART) The LSISAS1064 provides an industry standard UART interface. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or modem, and parallel-to-serial conversion on data characters received from the CPU ...
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... ICE JTAG post. The header has a 100 mil spacing between posts. The connector is a 20-way header that mates with IDC sockets that are mounted on a ribbon cable. This header enables LSI Logic to debug the board design. to include a header, route the ARM Multi-ICE signals to through-holes. ...
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... Functional Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Chapter 3 Signal Description This chapter describes the input and output signals of the LSISAS1064, and consists of the following sections: Section 3.1, “Signal Organization” Section 3.2, “PCI Signals” Section 3.3, “PCI-Related Signals” Section 3.4, “Compact PCI Signals” Section 3.5, “SAS Signals” ...
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... Output, a standard output driver (typically a Totem Pole output) Input and output (bidirectional) Power Ground contains the functional signal groupings of the LSISAS1064. on page 5-18 provides a diagram of the LSISAS1064 472 Ball Table 5.31 and Table 5.32 provide alphabetical and alphanumeric pin listings for the on page 5-13 ...
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... Figure 3.1 LSISAS1064 Functional Signal Grouping System Address and Data Interface PCI/PCI-X Bus Control Interface Arbitration Error Reporting Interrupt PCI Related Signals Compact PCI Interface Memory Interface Signal Organization Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. LSISAS1064 CLK ...
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... PAR AD9 PAR64 AB17 3-4 Signal Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. describes the PCI system signals. Type Description I Refer to the PCI Local Bus Specification, Version 3.0, and the PCI-X Addendum to the PCI Local Bus Specification, I Version 2 ...
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... PERR/ AF7 SERR/ AF3 PCI Signals Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. describes the PCI interface control signals. Description I/O Refer to the PCI Local Bus Specification, Version 3.0, and the PCI-X Addendum to the PCI Local Bus Specification, I/O Version 2 ...
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... ZCR implementations. – The active LOW ZCR enable input configures the LSISAS1064 for Zero Channel RAID operation. When this input is asserted, the standard PCI signals INTA/ and GNT/ are not used, and the alternate signals ALT_INTA/ and ALT_GNT/ are used. When this input is deasserted, the chip is confi ...
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... Asserting active LOW CompactPCI Enable configures the LSISAS1064 for the CompactPCI protocol. I The active HIGH CompactPCI Switch signal indicates to the LSISAS1064 that a change in the system configuration is imminent. The CompactPCI device insertion/removal mechanism controls the assertion of this signal. I/O This signal informs the system of a board removal or insertion. ...
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... MOE[1]/ enables Flash ROM devices. MOE[0]/ enables NVSRAM devices. MOE[1:0]/ allow interleaved PSBRAM configurations. O The LSISAS1064 uses the active LOW Memory Bank Write Enable signals for interleaved PSBRAM configurations. Asserting the active LOW Byte-lane Write Enable signals enable partial word writes to the PSBRAM ...
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... PSBRAMs. The LSISAS1064 supports up to four PSBRAMs in an interleaved and depth-expanded configuration. O Asserting the active LOW Flash Chip Select signal selects the Flash ROM. The LSISAS1064 maps the Flash ROM address space into system memory. 2 describes the UART and I Description ...
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... Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. describes the configuration and general purpose signals. I Asserting the Test Reset signal forces the chip into a Power-On-Reset state. The LSISAS1064 does not contain an internal power-on reset circuit. This signal must be supplied by a power-on reset circuit on the board. I This pin provides the ARM reference clock ...
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... SCAN_ENABLE B2 SCAN_MODE H7 TMUX_SPARE[7:0] F6, C3, B3, D4, C4, E6, A2, A3 RESERVED V4, W3 JTAG and Test Signals Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. describes the test and JTAG signals. Description I JTAG Debug Clock. I JTAG Debug Reset. I JTAG Debug Test Data In. ...
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... P These signals provide 3.3 V PCI I/O power. P These signals provide the bias reference for PCI pads. Connect this signal to 3.3 V. The LSISAS1064 does not support 5 V PCI. G These signals provide ground. G These signals provide ground for the GigaBlaze core of each respective phy. ...
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... Power-On Sense Pins Description This section discusses the power-on sense pin configuration options. For setting global operating conditions, the LSISAS1064 uses power-on sense register bits that source their data from the state of the memory address/data bus (MAD[31:0]) during the device boot up sequence. The MAD signals are 3-stated and read continuously during PCI reset, and are latched upon removal of the PCI reset signal ...
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... MAD[29] SGPIO CPLD Installed – Pulling this signal LOW indicates that an SGPIO CPLD is not installed. Pulling this signal HIGH indicates that an SGPIO CPLD is installed. 3-14 Signal Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Pulled LOW (Default) No NVSRAM/SRAM installed NVSRAM/SRAM installed SRAM Installed SGPIO CPLD not installed ...
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... Device ID register to 0b0. Pulling this signal HIGH programs bit 0 of the Device ID register to 0b1. MAD[2:1], Flash ROM Size – These pins configure the Flash ROM size. Power-On Sense Pins Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Subsystem ID register description on 3-15 ...
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... REFCLK_B D3 FSELA G5 TST_RST/ G7 3-16 Signal Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. describes the pull-up and pull-down signals for the LSISAS1064. Pull Type Internal Pull-down. Internal Pull-down. Internal Pull-up. Internal Pull-up. Internal Pull-up. Internal Pull-up. Internal Pull-up. ...
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... Management, Messaged Signaled Interrupts, MSI-X, and PCI-X) to optimize device performance. The LSISAS1064 does not hard code the location and order of the PCI extended capability structures. The address and location of the PCI extended capability structures are subject to change. To access a PCI ...
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... Pointer registers and identify the extended capability structure with the Capability ID register for the given structure. Table 4.1 LSISAS1064 PCI Configuration Space Address Map 31 Device ID Status Class Code Reserved Header Type Subsystem ID Expansion ROM Base Address Reserved Maximum Latency Minimum Grant ...
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... The Command register provides coarse control over the PCI function’s ability to generate and respond to PCI cycles. Writing a zero to this register logically disconnects the LSISAS1064 PCI function from the PCI bus for all accesses except configuration accesses. Reserved This field is reserved. ...
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... Setting this bit enables the LSISAS1064 PCI function to detect parity errors on the PCI bus and report these errors to the system. Clearing this bit causes the LSISAS1064 PCI function to set the Detected Parity Error bit, bit 15 in the PCI Status register, but not assert PERR/ when the PCI function detects a parity error ...
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... Version 3.0, and PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0. Signaled System Error The LSISAS1064 PCI function sets this bit when asserting the SERR/ signal. Received Master Abort (from Master) A master device sets this bit when a Master Abort command terminates its transaction (except for Special Cycle) ...
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... LSISAS1064 PCI function is capable of operating at 66 MHz. Pulling MAD[13] HIGH clears this bit and indicates to the host system that the LSISAS1064 PCI function is not configured to operate at 66 MHz. Refer to Section 3.11, “Power-On Sense Pins Description,” ...
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... New Capabilities The LSISAS1064 PCI function sets this read only bit to indicate a list of PCI extended capabilities such as PCI Power Management, MSI, MSI-X, and PCI-X support. Interrupt Status This bit reflects the status of the INTA/ (or ALT_INTA/) signal. Reserved This field is reserved. Register: 0x08 ...
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... The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. If the LSISAS1064 initializes in the PCI mode, the default value of this register is 0x00. If the LSISAS1064 initializes in the PCI-X mode, the default value of this reg- ister is 0x40. ...
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... This base address register maps the operating register set into I/O Space. The LSISAS1064 requires 256 bytes of I/O Space for this base address register. Hardware sets bit 0 to 0b1. Bit 1 is reserved and returns 0b0 on all reads. PCI Configuration Space Register Description Copyright © ...
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... Memory Space [0] base address. Hardware programs bits [9:0] to 0b0000000100, which indicates that the Memory Space [0] base address is 64 bits wide and that the memory data is not prefetchable. The LSISAS1064 requires 1024 bytes of memory space. Register: 0x18–0x1B Memory [0] High ...
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... Memory Space [1] base address. Hardware programs bits [12:0] to 0b0000000000100, which indicates that the Memory Space [1] base address is 64 bits wide and that the memory data is not prefetchable. The LSISAS1064 requires 64 Kbytes of memory for Memory Space [1]. Register: 0x20–0x23 Memory [1] High ...
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... Subsystem Vendor ID This 16-bit register uniquely identifies the vendor that manufactures the add-in board or subsystem where the LSISAS1064 resides. This register provides a mecha- nism for an add-in card vendor to distinguish their cards from another vendor’s cards, even if the cards use the same PCI controller (and have the same Vendor ID and Device ID) ...
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... PCI controller (and have the same Vendor ID and Device ID). The board designer can store a vendor specific, 16-bit value in the NVData image. By default, the LSISAS1064 loads this register from the NVData image at power up. The Subsystem Device ID Control Power-On Sense pin (MAD[5]) can control the value of bit [15] of this register ...
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... ROM base address. The host system detects the size of the external memory by first writing 0xFFFFFFFF to this register and then reading the register back. The LSISAS1064 responds with zeros in all don’t care locations. The least significant one (1) that remains represents the binary version of the external memory size ...
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... Register: 0x35–0x37 Reserved Register: 0x38–0x3B Reserved Register: 0x3C Interrupt Line Read/Write 7 0 PCI Configuration Space Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved Reserved Reserved This register is reserved Reserved Reserved This register is reserved. Interrupt Line ...
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... ALT_INTA/, or both. Minimum Grant Min_Gnt This register specifies the desired settings for the latency timer values in units of 0.25 s. Min_Gnt specifies how long of a burst period the device needs. The LSISAS1064 sets this register to 0x40 indicating a burst period of 16.0 s. Maximum Latency ...
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... This register specifies the desired settings for the latency timer values in units of 0.25 s. Max_Lat specifies how often the device needs to gain access to the PCI bus. The LSISAS1064 sets this register to 0x0A since it requires the PCI bus every 2.5 s. Register: 0xXX ...
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... Reserved This bit is reserved. PME Clock The LSISAS1064 clears this bit since the chip does not provide a PME pin. Version The PCI function programs these bits to 0b010 to indicate that the LSISAS1064 complies with the PCI Power Management Interface Specifi ...
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... Data_Select The PCI function clears these bits since the LSISAS1064 does not support the Power Management Data register. PME_Enable The PCI function clears this bit since the LSISAS1064 does not provide a PME signal and disables PME assertion. Reserved This field is reserved. ...
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... Power Management Data Power Management Data This register provides an optional mechanism for the PCI function to report state-dependent operating data. The LSISAS1064 always returns 0x00 in this register. MSI Capability MSI Capability ID This register indicates the type of the current data structure. This register always returns 0x05, indicating Message Signaled Interrupts (MSI) ...
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... Multiple Message Enable These read/write bits indicate the number of messages that the host allocates to the LSISAS1064. The host system software allocates all or a subset of the requested messages by writing to this field. The number of allocated request messages must align to a power of two. ...
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... LSISAS1064 requests from the host. The host system software reads this field to determine the number of requested messages. The number of requested messages must align to a power of two. The LSISAS1064 sets this field to 0b000 to request one message. All other encodings of this field are reserved. ...
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... MSI Message Data System software initializes this register by writing to it. The LSISAS1064 sends an interrupt message by writing a Dword to the address held in the Address and MSI Message Upper Address register forms bits [15:0] of the Dword message that the PCI function passes to the host. The PCI function drives bits [31:16] of this message to 0x0000 ...
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... Register: 0xXX MSI-X Capability ID Read Only 7 0 4-24 PCI Host Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved MSI Mask Bits MSI Mask Bits For each mask bit that is set, the device is prohibited from sending an associated message. Refer to the PCI specifi ...
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... Reserved This field is reserved. Table Size Host software reads this field to determine the MSI-X table size. PCI Configuration Space Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. MSI-X Next Pointer ...
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... Table 4.3 BIR Value 4-26 PCI Host Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved MSI-X Table Offset MSI-X Table Offset This field provides an offset from the address held in the base address registers of the device to the base of the MSI-X table ...
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... Register: 0xXX PCI-X Capability ID Read Only 7 0 PCI Configuration Space Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved MSI-X PBA Offset MSI-X PBA Offset This field contains an offset from one of the base address registers of the device that points to the MSI-X PBA. The lower 3 bits of this register are cleared (‘ ...
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... LSISAS1064 can have outstanding at one time. The LSISAS1064 uses the most recent value of this register each time it prepares a new sequence. Note that if the LSISAS1064 prepares a sequence before the setting of this field changes, the PCI function initiates the prepared sequence with the previous setting. ...
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... Data Parity Error Recovery Enable The host device driver sets this bit to allow the LSISAS1064 to attempt to recover from data parity errors. If the user clears this bit and the LSISAS1064 is operating in the PCI-X mode, the LSISAS1064 asserts SERR/ whenever the Master Data Parity Error bit in the ...
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... Reserved This field is reserved. Received Split Completion Error Message The LSISAS1064 sets this bit upon receipt of a split completion message if the split completion error attribute bit is set. Write a one (1) to this bit to clear it. Designed Maximum Cumulative Read Size These read only bits indicate a number greater than or ...
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... Allowing the internal pull-downs to pull MAD[14] LOW sets this bit and indicates a 64-bit PCI Address/Data bus. Pulling MAD[14] HIGH clears this bit and indicates a 32-bit PCI Address/Data bus. If using the LSISAS1064 on an add-in card, this bit must indicate the size of the card’s PCI Address/Data bus. Refer to Sense Pins Description,” ...
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... Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Device Number These read only bits indicate the device number of the LSISAS1064. The PCI function uses this number as part of its Requester ID and Completer ID. This field is read for diagnostic purposes only. Function Number These read only bits indicate the number in the Function Number fi ...
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... PCI Memory [1] Address Map 31 A bit level description of the PCI Memory and PCI I/O Spaces follows. PCI I/O Space and Memory Space Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. PCI I/O Space Address Map 16 15 System Doorbell ...
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... IOP processor and vice versa. When a host system PCI master writes to the Host Registers->Doorbell register, the LSISAS1064 generates a maskable interrupt to the IOP. The value written by the host system is available for the IOP to read in the System Interface Registers->Doorbell register. The IOP clears the interrupt status after reading the value ...
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... Reserved This field is reserved. Clear Flash Bad Signature Writing a one (1) to this bit clears the Flash Bad Signature setting within the LSISAS1064. This bit is self-clearing. Prevent IOC Boot Setting this bit prevents the IOP from rebooting after a reset. Reserved This field is reserved. ...
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... The LSISAS1064 maintains this state until the PCI host clears both the Flash Bad Signature and DisARM bits. Reset History The LSISAS1064 sets this bit if it experiences a Power On Reset (POR), PCI Reset, or TestReset/. Diagnostic Read/Write Enable Setting this bit enables access to the ...
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... This register reads or writes Dword locations on the LSISAS1064 internal bus. This register is only accessible through PCI I/O Space and returns 0xFFFFFFFF if read through PCI Memory Space. The host can enable write access to this register by writing the correct Write I/O Key to the ...
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... Host Interrupt Status IOP Doorbell Status The LSISAS1064 sets this bit when the IOP receives a message from the system doorbell but has yet to process it. The IOP processes the System Doorbell message then clears the corresponding system request interrupt ...
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... Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Reserved This field is reserved. Reply Interrupt The LSISAS1064 sets this bit when the Reply Post FIFO is not empty. The LSISAS1064 generates a PCI interrupt when this bit is set and the corresponding mask bit in the Host Interrupt Mask register is cleared ...
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... The Request Queue accepts Request Post MFAs from the host system on writes. 4-40 PCI Host Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Interrupt Signal Routing INTA/ and ALT_INTA/ INTA/ Only ALT_INTA/ Only INTA/ and ALT_INTA/ Reserved This fi ...
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... The High Priority Request Queue accepts High Priority Request Post MFAs from the host on writes. The High Priority Request Post Queue is similar to the Request Post Queue, except that the LSISAS1064 processes requests from the High Priority Request Post FIFO before processing requests from the Request Post Queue. ...
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... PCI Host Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Section 5.5, “Package Drawings” Please refer to the PCI Local Bus Specification, the PCI-X Addendum to the PCI Local Bus Specification, and the Serial Attached SCSI Standard for timing information. The LSISAS1064 timings conform to the information that these specifications provide. 5.1 ...
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... Core and analog supply only. 3. These numbers are specified for the design of the I/O power network. Not all of the I to the LSISAS1064 dissipates on-chip. For more information concerning the SAS/SATA transceivers, please refer to the Serial Attached SCSI specification. Table 5.3 GigaBlaze Transmitter Voltage Characteristics – ...
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... CPCI_ENUM/, PAR, PAR64, ACK64/, REQ64/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, SERR/ Parameter Min V -0 0.5 VDDIO ih DC Characteristics Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Max Unit – mV – mV Nominal Fall Specified Time Range 153 67 - 273 ...
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... Parameter VT+ VT- Hysteresis pull-up 5-4 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. PCI-X Bidirectional Signals – AD[63:0], C_BE[7:0]/, CPCI_ENUM/, PAR, PAR64, ACK64/, REQ64/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, SERR/ (Cont.) Min Max – 0.1 ol 0.9 ...
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... Parameter Min V – 2 -10 oz Table 5. Outputs – UART_TX Parameter Min V – 2 - Characteristics Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Nom Max 1.6 2 1.2 – 0.4 – – 10 140 350 Max 0.4 – 10 Max 0.4 – 10 Max 0.4 – 10 Max 0 ...
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... Table 5.17 Parameter Table 5.18 Parameter I pull-down Table 5.19 Parameter I pull-up Table 5.20 Parameter 5-6 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved Outputs – PROCMON Min V – 2 - Bidirectional Signals – MAD[31:0] Min V VSS - 0 – 2 - Bidirectional Signals – MADP[3:0] ...
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... I - Table 5.23 Capacitance Capacitance (PCI-X pads Capacitance values do not include package capacitance. DC Characteristics Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Max 0.8 VDD + 0.3 0.4 – 10 200 Nominal Max 2.0 2.4 – 2.0 – 2.1 – 3.4 – ...
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... For frequencies above 33 MHz, the clock frequency can not be changed beyond the spread spectrum limits except while RST/ is asserted. 2. Duty cycle not to exceed 60/40. 5-8 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. Figure 5.1 External Clock ...
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... CLK HIGH to IRQ/ LOW 1 t CLK HIGH to IRQ/ HIGH 2 t IRQ/ deassertion time 3 AC Characteristics Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. and Table 5.25 provide reset input timing data. Reset Input t 1 and Table 5.26 provide Interrupt Output timing data. ...
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... External Memory Timing Diagrams This section provides timing information and examples for the external memory options available for use with the LSISAS1064. Table 5.27 Flash Write Timing Parameters Symbol Parameter t Flash Address Setup to FLASH_CS/ (Write Flash Address Setup to BWE/ (Write Enables) ...
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... NVRAM_CS/ Width (Read NVRAM Read Recover (back-to-back access) 3 – NVRAM Read Cycle Time Figure 5.6 NV Read MA A(00) MD[31:24 NVRAMCS/ MOE0/ BWE2/ External Memory Timing Diagrams Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. A(01) A(10 A(01) A(10 A(11) A=4(00 ...
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... A(00) MD[31:24 NVRAMCS BWE2/ MOE/ 5.4 Pinout Table 5.31 the BGA pin listing. 5-12 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. A(01) A(10 provides the signal listing by signal name. Figure 5.8 provides a BGA diagram. Min Max ...
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... AD[51] AE24 MAD[3] AD[52] AF24 MAD[4] AD[53] AB19 MAD[5] AD[54] AD22 MAD[6] Note: NC pins are not connected. Pinout Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. SignalPin AD23 MAD[7] D24 AF22 MAD[8] D25 AF23 MAD[9] E25 AE22 MAD[10] C26 ...
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... SERIAL_DATA A7 VDD2 SERR/ AF3 VDD2 STOP/ AE6 VDD2 TCK L2 VDD2 TCK_ICE B5 VDD2 Note:NC pins are not connected. 5-14 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. SignalPin J1 VDDIO33 C6 F7 VDDIO33 C7 M23 VDDIO33 E4 K26 VDDIO33 E5 K1 VDDIO33 E22 B4 ...
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... E16 C8 N/C E17 C9 RTRIM E18 C10 TXB_VSS3 E19 C11 VDD2 E20 Note: NC pins are not connected. Pinout Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. SignalPin VDD2 E21 TX2 E22 N/C E23 N/C E24 RX2 E25 RXB_VDD2 E26 TX_VDD1 ...
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... W2 N/C AB11 W3 N/C AB12 W4 N/C AB13 W5 RST/ AB14 Note: NC pins are not connected. 5-16 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. SignalPin N/C AB15 VSS2 AB16 AD[37] AB17 N/C AB18 VDDIO5PCIX N/C AB19 MADP[3] AB20 VDDIO5PCIX ...
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... Pinout Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. 5-17 ...
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... Figure 5.8 LSISAS1064 472-Pin BGA Top View TMUX_ TMUX_ SPARE[1] SPARE[0] TMS_ICE SCAN_ TMUX_ VSS2 ENABLE SPARE[5] TDO_ICE REFPLL_ TMUX_ TMUX_ VSS MODE[5] SPARE[6] SPARE[ REFPLL_ TMUX_ MODE[3] VDD REFCLK_B SPARE[ FAULT_ LED[1]/ MODE[1] MODE[2] VDDIO33 FAULT_ FAULT_ LED[3]/ LED[0]/ MODE[0] ...
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... Figure 5.8 LSISAS1064 472-Pin BGA Top View (Cont.) A14 A15 A16 A17 RX3 TX_VSS2 N/C TXB_VSS2 B14 B15 B16 B17 VSS2 VSS2 RX2+ RX_VSS2 C14 C15 C16 C17 N/C N/C RX2 RXB_VDD2 D14 D15 D16 D17 N/C N/C N/C VSS2 E14 ...
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... Package Drawings The LSISAS1064 is packaged in a 472-EPBGA-T package with footprint and 1.0 mm ball pitch. The package code is UO. The package drawing number is JZ02-000015-00. provides the package diagram for the LSISAS1064. 5-20 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... EPBGA-T (UO) Mechanical Drawing (Sheet Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO. Package Drawings Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... EPBGA-T (UO) Mechanical Drawing (Sheet (Cont.) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO. 5-22 Specifications ...
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... EPBGA-T (UO) Mechanical Drawing (Sheet (Cont.) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO. Package Drawings Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... I/O Base Address Memory [0] Low Memory [0] High Memory [1] Low Memory [1] High Reserved Subsystem Vendor ID Subsystem ID LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. A.3 provide a register summary. 1 Offset 0x00–0x01 0x02–0x03 0x04– ...
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... Table A.1 LSISAS1064 PCI Configuration Space Registers (Cont.) Register Name Expansion ROM Base Address Capabilities Pointer Reserved Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Power Management Capability ID Power Management Next Pointer Power Management Capabilities Power Management Control/Status Power Management Bridge Support Extensions – ...
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... Table A.1 LSISAS1064 PCI Configuration Space Registers (Cont.) Register Name MSI-X Table Offset MSI-X PBA Offset PCI-X Capability ID PCI-X Next Pointer PCI-X Command PCI-X Status 1. The offset of the PCI extended capabilities registers can vary. Access these registers through the Next Pointer and Capability ID registers. ...
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... Table A.3 LSISAS1064 PCI Memory [0] Space Registers Register Name System Doorbell Write Sequence Host Diagnostic Test Base Address Reserved Host Interrupt Status Host Interrupt Mask Reserved Request Queue Reply Queue High Priority Request MFA Queue A-4 Register Summary Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... ARM966E-S 1-3, 2-4, 4-36 aux_current bit 4-18 LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. B ball grid array 5-18, 5-8 base address register I/O 2-4, memory [0] memory [1] ...
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... IX-2 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. capability ID MSI 4-20, PCI-X 4-4 power management capacitance class code register CLK 3-4, 4-39 ...
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... ESD 5-2 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. expansion ROM base address 4-30 expansion ROM base address register expansion ROM enable bit external clock memory interface ...
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... IOP boot enable 3-14, 3-15 IOP doorbell status bit 4-38 IRDY/ 3-5, 5-3 ISTW_CLK 3-9 IX-4 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ISTW_DATA ISTWI_CLK 3-16, ISTWI_DATA 3-16, 4-9 J junction temperature K key I/O 4-35, 4-36, L latch-up current ...
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... MWE[1:0]/ 3-8, 5-6 N narrow port 2-17 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. NC 3-1, 3-13 new capabilities bit no connect NVSRAM NVSRAM or SRAM select NVSRAM/SRAM installed NVSRAM_CS/ 3-8, O operating conditions ...
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... IX-6 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. memory space [1] 2-10, memory write and invalidate command 2-11, 2-12 2-14, memory write block command 2-12, 2-13 ...
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... D0 2-16 D1 2-16 D2 2-16 D3 2-16, 4-19 power state bit 4-19 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. 4-31 power-on reset power-on sense pins 4-31 PROCMON 3-11, PSBRAM_CS/ 3-9, pull-ups and pull-downs Q 4-21 queue message reply ...
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... MFA 4-41 IX-8 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. reply post FIFO 2-4, 2-8, reply queue reply queue register REQ/ 3-5, REQ64/ 3-5, request free FIFO request message frames 2-8, ...
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... PLL_VSS 3-12 power-on sense 3-13 PROCMON 3-11 PSBRAM_CS/ 3-9 REFCLK 3-7 REFCLK_B 3-10 REFPLL_VDD 3-12 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. REFPLL_VSS 3-12 REQ/ 3-5 REQ64/ 3-5 RST/ 3-4 RTCK_ICE 3-11 RTRIM 3-7 RX[3:0]- 3-7 RX[3:0]+ ...
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... TCK 3-11, 3-16, 5-4 TCK_ICE 3-11, 3-16, 5-4 IX-10 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. TDI 3-11, 3-16, TDI_ICE 3-11, 3-16, TDIODE_N TDIODE_P TDO 3-11, TDO_ICE 3-11, temperature junction operating free air ...
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... I/O key 4-35, 4-36, 4-38 write sequence register 4-34, 4-36, Z ZCR 2-23, 2-24 ZCR_EN/ 2-23, 3-6, 3-16, 5-4 zero channel RAID 2-23, 2-24 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. 4-4 4-38 IX-11 ...
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... IX-12 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved. ...
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... Reader’s Comments Fax your comments to: Please tell us how you rate this document: LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller, Version 3.2. Place a check mark in the appropriate blank for each category. Completeness of information Clarity of information Ease of finding information Technical content Usefulness of examples and ...