LSISAS1064 LSI, LSISAS1064 Datasheet - Page 97

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

Table 4.4
Table 4.5
PCI Configuration Space Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Bits [6:4]
Encoding
0b011
0b100
0b101
0b110
0b111
Bits [3:2]
Encoding
0b00
0b01
0b10
0b11
Maximum Outstanding Split Transactions (Cont.)
Maximum Memory Read Count
Maximum Memory Read Byte Count
These bits indicate the maximum byte count the
LSISAS1064 uses when initiating a sequence with one of
the burst memory read commands.
the bit encodings for this field.
Reserved
This bit is reserved.
Data Parity Error Recovery Enable
The host device driver sets this bit to allow the
LSISAS1064 to attempt to recover from data parity
errors. If the user clears this bit and the LSISAS1064 is
operating in the PCI-X mode, the LSISAS1064 asserts
SERR/ whenever the Master Data Parity Error bit in the
PCI
Maximum Memory Read Byte Count
Maximum Outstanding
Status
Split Transactions
Reserved
register is set.
12
16
4
8
Reserved
1024
2048
512
Table 4.5
provides
[3:2]
4-29
1
0