LSISAS1064 LSI, LSISAS1064 Datasheet - Page 60

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

3.6
Table 3.10
3-8
Signal Name BGA Position
MCLK
ADSC/
ADV/
MAD[31:0]
MADP[3:0]
MOE[1:0]/
MWE[1:0]/
BWE[3:0]/
NVSRAM_CS/ G26
Memory Interface Signals
Memory Interface Signals
N26
P23
U26
AB26, AA25, R22,
W26, V24, V25,
AA26, U24, T22,
Y26, R23, U25,
R26, T24, T26, V26,
H24, K24, H23,
H21, D23, C26,
E25, D25, D24,
D26, E24, C24,
C25, G23, F23, B26
W23, P26, J26, G21 I/O
E26, M22
H25, L26
N25, J25, M26, N22 O
Table 3.10
Signal Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
describes the memory interface signals.
Type Description
O
O
O
I/O
O
O
O
All synchronous RAM control/data signals reference the
rising edge of the Memory Clock signal. MOE[1:0]/ are
asynchronous inputs and do not reference this clock.
Asserting the active LOW Address-Strobe-Controller
signal initiates read, write, or chip deselect cycles.
Asserting the active LOW Advance signal increments the
burst address counter of the selected synchronous SRAM.
The Multiplexed Address/Data bus signals provide the
address and data bus to the PSBRAM, Flash ROM, and
NVSRAM.
These signals also provide Power-On Sense configuration
functions to the LSISAS1064.
Sense Pins Description,”
configuration options.
Provide both pull-down and pull-up resistors for these pins.
The Multiplexed Address/Data Parity signals provide
parity checking for MAD[31:0]. MADP[3] provides parity
protection for the high-order byte (MAD[31:24]). while
MADP[0] provides parity protection for low-order byte
(MADP[7:0]).
Asserting the active LOW Memory Output Enable signals
enable the selected PSBRAM, Flash ROM, or NVSRAM
device to drive data. MOE[1]/ enables Flash ROM devices.
MOE[0]/ enables NVSRAM devices. MOE[1:0]/ allow
interleaved PSBRAM configurations.
The LSISAS1064 uses the active LOW Memory Bank
Write Enable signals for interleaved PSBRAM
configurations.
Asserting the active LOW Byte-lane Write Enable signals
enable partial word writes to the PSBRAM. BWE[3]/ and
BWE[2]/ enable partial word writes to the Flash ROM
and/or the NVSRAM if FLASH_CS/ or NVSRAM_CS/ are
asserted.
Asserting the active LOW NVSRAM Chip Select signal
selects the NVSRAM.
describe the Power-On sense
Section 3.11, “Power-On