LSISAS1064 LSI, LSISAS1064 Datasheet - Page 31

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LSISAS1064

Manufacturer Part Number
LSISAS1064
Description
Manufacturer
LSI
Datasheet

Specifications of LSISAS1064

Lead Free Status / RoHS Status
Not Compliant

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2.1.1.4
2.1.1.5
2.1.1.6
2.1.1.7
2.1.1.8
PCI Timer and Configuration
Timer and Configuration
DMA Arbiter
External Memory
I
2
C
This PCI Timer and Configuration module supports the PCI configuration
register space, an industry-standard and a power-on reset (POR).
This block supports the LSISAS1064 LED and GPIO interfaces. There
are a total of nine LED signals on the LSISAS1064. Each of the four phys
has an LED signal to indicate activity on the link and an LED signal to
indicate an error on the link. The GPIO interface contains four
independent GPIO signals. The LED signals can also be configured as
GPIO signals. This block provides an firmware heartbeat LED. This block
also supports internal timing adjustments and power-on sense
configuration options.
The LSISAS1064 provides the ability to transfer system memory blocks
to and from local memory through the descriptor-based DMA arbiter and
router.
The external memory controller block provides an interface for Flash
ROM, NVSRAM, and PSBRAM devices. The external memory bus
provides a 32-bit memory bus, parity checking, and chip select signals
for PSBRAM, NVSRAM, and Flash ROM.
Typical system configurations require a Flash ROM to store firmware,
configuration information, and persistent data information.
The LSISAS1064 contains an Inter-IC (I
with peripherals. This interface is also referred to as an industry standard
2-wire interface (ISTWI). The I
slave on the bus and sustains data rates up to 400 Kbits/s. The I
accomplishes byte-wise bidirectional data transfers by using either an
interrupt or a polling handshake at the completion of each byte. The style
and operation of this interface closely follows the de facto standard for a
Block Diagram Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
2
C block operates as either a master or a
2
C) interface that communicates
2
C block
2-5

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