LSISAS1064 LSI, LSISAS1064 Datasheet - Page 37

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

Table 2.1
1. The LSISAS1064 ignores reserved commands as a slave and never generates them as a master.
2. When acting as a slave in the PCI mode, the LSISAS1064 supports this command as the PCI
3. When acting as a slave in the PCI mode, the LSISAS1064 supports this command as the PCI
2.3.2.1
2.3.2.2
2.3.2.3
2.3.2.4
C_BE[3:0]/ PCI Command
0b1100
0b1101
0b1110
0b1111
Memory Read command.
Memory Write command.
Interrupt Acknowledge Command
Special Cycle Command
I/O Read Command
I/O Write Command
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
PCI/PCI-X Bus Commands and Encodings
The following sections describe how the LSISAS1064 implements these
commands.
The LSISAS1064 ignores this command as a slave and never generates
it as a master.
The LSISAS1064 ignores this command as a slave and never generates
it as a master.
The I/O Read command reads data from an agent mapped in the I/O
address space. When decoding I/O commands, the LSISAS1064
decodes the lower 32 address bits and ignores the upper 32 address
bits. The LSISAS1064 supports this command when operating in either
the PCI or PCI-X bus mode.
The I/O Write command writes data to an agent mapped in the I/O
address space. When decoding I/O commands, the LSISAS1064
decodes the lower 32 address bits and ignores the upper 32 address
bits. The LSISAS1064 supports this command when operating in either
the PCI or PCI-X bus mode.
PCI Functional Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
PCI-X Command
Split Completion
Dual Address Cycle
Memory Read Block
Memory Write Block
1
(Cont.)
as Master
Supports
Yes
Yes
Yes
Yes
Supports
as Slave
Yes
Yes
Yes
Yes
2
2
3
2-11