LSISAS1064 LSI, LSISAS1064 Datasheet - Page 20

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

1.4
1-6
Benefits of PCI-X
The Fusion-MPT architecture improves overall system performance by
requiring only a thin device driver, which off loads the intensive work of
managing I/Os from the system processor to the LSISAS1064. The use
of thin, easy to develop, common OS device drivers accelerates time to
market by reducing device driver development and certification times.
The Fusion-MPT architecture provides an interrupt coalescing feature.
Interrupt coalescing allows an I/O controller to send multiple reply
messages in a single interrupt to the host processor. Sending multiple
reply messages per interrupt reduces context switching of the host
processor and maximizes the host processor efficiency, which results in
a significant improvement of system performance. To use the interrupt
coalescing feature, the host processor must be able to accept and
manage multiple replies per interrupt.
The Fusion-MPT architecture also provides built-in device driver stability
since the device driver need not change for each revision of the
LSISAS1064 silicon or firmware. This architecture is a reliable, constant
interface between the host device driver and the LSISAS1064. Changes
within the LSISAS1064 are transparent to the host device driver,
operating system, and user. The Fusion-MPT architecture also saves the
user significant development and maintenance effort since it is not
necessary to alter or redevelop the device driver when a revision of the
LSISAS1064 device or firmware occurs.
PCI-X doubles the maximum clock frequency of the conventional PCI
bus. The PCI-X Addendum to the PCI Local Bus Specification,
Revision 2.0, defines enhancements to the proven PCI Local Bus
Specification, Revision 3.0. PCI-X provides more efficient data transfers
by enabling registered inputs and outputs, improves buffer management
by including transaction information with each data transfer, and reduces
bus overhead by restricting the use of wait states and disconnects. PCI-X
also reduces host processor overhead by providing a wide range of error
recovery implementations.
The LSISAS1064 supports up to a 133 MHz, 64-bit PCI-X bus and is
backwards compatible with previous versions of the PCI/PCI-X
specification. Per the PCI-X addendum, the LSISAS1064 includes
Introduction
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