LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 104

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

6-4
Examples:
1. A 40 MHz input clock and a maximum 400 kHz SCL output would
2. A 40 MHz input clock and a maximum 100 kHz SCL output would
Register: 0xFD00/0xFD02
Data (ES0, ES1, ES2 = 100)
Read/Write
D
Two-Wire Serial Registers
7
0
require D1*D0 to be greater than 100. A best fit would be for D1 to
be 32 and D0 to be 4. The value written into the register would be
0x15. This will yield a 312.5 kHz SCL output clock speed.
require D1*D0 to be greater than 400. A best fit would be for D1 to
be 128 and D0 to be 4. The value written into the register would be
0x16. This would yield a 78.125 kHz SCL output clock speed.
0
Data
This register is used for data transmission to and
reception from the Two-Wire Serial bus. During a transmit
operation, the data is sent out onto the Two-Wire Serial
bus after writing this register. During a receive operation,
this register must be read to request a byte from the slave
device. This prescribes a dummy read of this register to
ASF1
ICF2
0
0
1
1
0
1
1
1
1
0
ASF0
0
0
1
0
1
ICF1
0
0
1
1
x
D
0
1024
128
D1
16
32
ICF0
0
1
0
1
x
0
0
D0
2
3
4
5
8
0
0
[7:0]