LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 97

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Register: 0xFC23/0xFC2B
Physical Address (PHAD0/PHAD1)
Read Only
PA
Register: 0xFC24/0xFC2C
Live ESI (LESI0/LESI1)
Read Only
PESI/
DWR/
PESI/
7
x
7
x
Note:
DWR/
6
x
The RINT and WINT bits are not self-clearing, so the
microcontroller must clear this bit if the port is interrupt
driven.
x
are ORed together to generate the port interrupt, which
goes to the microcontroller using the
(ISR)
Physical Address
The Physical Address registers are read only registers
that contain values of the PA inputs.
PARALLEL_ESI/ Value
Reading this active low bit gives the state of the PESI/
signal, which is used to select between the SEL_ID and
the bidirectional interface that distinguishes the SFF-8067
interface from SFF-8045.
DSK_WR/ Value
Reading this active low bit gives the state of the
DSK_WR/ signal on the SFF-8067 interface. When this
active low bit is cleared, the drive is ready to write data
to the LSI53C040. It will be cleared (0) if the PESI/ bit is
cleared (0). If PESI/ is 1, this bit reflects the value of the
PA6 signal.
RD/
register.
5
x
x
ACK/
4
x
x
PA
D3
3
x
x
D2
2
x
x
Interrupt Status
D1
1
x
x
D0
0
0
x
x
[7:0]
5-5
7
6