LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 48

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.10.2.2 SCSI Bus Reset Interrupt
2.10.2.3 Parity Error Interrupt
2.10.2.4 Bus Phase Mismatch Interrupt
2-30
For send operations, the End of DMA bit is set when the DMA finishes
its transfer, but the SCSI transfer may still be in progress. If connected
as a target, REQ/ and ACK/ should be sampled until both are false. In
the LSI53C040 SCSI core, the Last Byte Sent (bit 7 of the
Command (TC)
byte was transferred.
The SCSI core generates an interrupt when the RST/ signal transitions
to asserted. The device releases all bus signals within a bus clear delay
(800 ns) of this transition. This interrupt also occurs after setting the
Assert RST/ bit (bit 7 of register 0xFC01).
An interrupt is generated for a received parity error if the Enable Parity
Check bit (bit 5) and the Enable Parity Interrupt bit (bit 4) are set in the
Mode (MR)
Current SCSI Data (CSD)
operation. A parity error can be detected without generating an interrupt
by disabling the Enable Parity Interrupt bit and checking the Parity Error
flag (bit 5 in register 0xFC05).
The SCSI phase lines are the I_O/, C_D/, and MSG/ bus signals. These
signals are compared with the corresponding bits in the
(TC)
(bit 2). The comparison occurs continually and is reflected in the Phase
Mismatch bit (bit 3) of the
DMA Mode bit (bit 1 in register 0xFC02) is active and a phase mismatch
occurs when REQ/ transitions from HIGH to LOW, an interrupt (IRQ) is
generated.
Functional Description
Note:
register: Assert I_O/ (bit 0), Assert C_D/ (bit 1), and Assert MSG/
register (0xFC02). Parity is checked during a read of the
The RST/ signal is not latched in bit 7 of the
Bus Status (CSBS)
this bit is read. For this case, the Bus Reset interrupt may
be determined by default.
register) may be sampled to determine when the last
Bus and Status (BSR)
register (0xFC00) and during a DMA receive
register and may not be active when
register (0xFC05). If the
Target Command
Current SCSI
Target