LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 42

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.9 SFF-8067 Mode
2-24
If the watchdog timer is used and it expires, it causes an internal soft
reset. If the Enable Reset Output bit is also set (0xFF05, bit 7), the
RESET/ pin is asserted low (0) to reset external devices. The Watchdog
Reboot bit is set (0xFE00, bit 7) to indicate that the LSI53C040 has
performed a soft reset due to expiration of the watchdog timer. Not all
register values in the LSI53C040 are affected by a soft reset. The
following bits/registers require a power-on reset to return to their default
values:
The two SFF-8067 interfaces allow the LSI53C040 to communicate with
Fibre Channel SCA-2 devices. Details of the protocol are provided in the
SFF-8067 specification.
The SFF-8067 port 0 and port 1 interfaces can be controlled either
manually by the microcontroller through direct control of the interface
pins; or automatically by the SFF-8067 interface control logic, which has
the ability to interrupt the microcontroller when input data has been
received over one of the ports or when output data has been requested
at one of the ports.
The SFF-8067 interface is enabled when the DIFFSENS pin is set to
V
Chapter
A simple ping-pong arbitration scheme provides equal priority access
between the two ports, since only one of them can be active at a time.
A drive requests access to the LSI53C040 by asserting the PARALLEL
ESI/ pin on its respective port. If the other port is not being used, the
Discovery and Data Transfer phases can proceed as described in the
Functional Description
DD
. The SCSI pins are reassigned to SFF-8067 pins, as indicated in
0xFE00,
0xFE02,
0xFF03,
Bit 7, Enable Reset Output, in register 0xFF05,
(SYSCTRL)
3.
Power-On Configuration One (POC1)
Watchdog Timer Control (WDTC)
Watchdog Final Chain (WDFC)
System Control