LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 123

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Register: 0xFE0C
Timer 2 Final Chain (T2FC)
Read Only
T2FC
Register: 0xFE0D
Interrupt Mask (IMR)
Read/Write
These register bits provide the ability to mask the corresponding
interrupts in the
a bit in this register enables the corresponding interrupt in the ISR
register.
IMR7
IMR6
IMR5
IMR7
7
0
7
0
IMR6
0
6
0
Timer 2 Final Chain
These register bits provide the ability to read the final
timer 2 divider chain. The expiration condition for this
timer is when the value of this divider chain is equal to
the value of the
(0xFE0A). When this happens, the T2EXP bit (0xFE09,
bit 7) will be set and an interrupt will be generated to the
microcontroller, through the
(0xFE04), if the T2IEN bit (0xFE09, bit 0) is set.
SCSI Interrupt
Clearing this bit masks this interrupt. Setting this bit
enables the interrupt.
Two-Wire Interface 1 Interrupt
Clearing this bit masks this interrupt. Setting this bit
enables the interrupt.
Two-Wire Interface 0 Interrupt
Clearing this bit masks this interrupt. Setting this bit
enables the interrupt.
Interrupt Status (ISR)
IMR5
0
5
0
IMR4
0
4
0
Timer 2 Threshold (T2T)
T2FC
IMR3
register (0xFE04). Writing a 1 to
0
3
0
Interrupt Status (ISR)
IMR2
0
2
0
IMR1
register
0
1
0
register
IMR0
0
0
0
0
[7:0]
7-13
7
6
5