LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 207

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

registers (Cont.)
repeated start bit
REQ bit
REQ/ handshake
request bit
reset parity/interrupt register
reset pin
resets
REV[3:0] bits
RINT bit
ROM download
RPI register
RPSS bit
RRF bit
RST bit
S
SAF-TE typical implementation
SBR[1:0] bits
SCLI0 bit
SCLI1 bit
SCLO0 bit
SCLO1 bit
SCSI arbitration
SCSI core
SCSI current SCSI data bus bits
SCSI high ID bits
SCSI high IDs
SCSI interrupt bit 7-7,
SCSI interrupts
SCSI isolation bit
SCSI LVD mode bit
SCSI output data bus bits
SCSI pins
SCSI protocol
SCSI reselection
SCSI reset bit
SCSI selection
SCSI_INT bit
SCSI-DMA transfers
SDAI0 bit
SDAI1 bit
SDAO0 bit
SDAO1 bit
SDIR register
SDTR register
SE[7:0] bits
SEL bit
select bit
select enable register
select enable register high
selection ID bits
WDATA0–WDATA1
WDFC
WDSC
WDTC
write data
description
halting a DMA operation
interrupts
overview
register bits used for interrupts
SCSI-DMA transfers
timings
register bits used
2-23
4-10
4-9
5-4
4-9
5-4
2-23
4-10
6-7
6-10
6-9
6-10
6-9
3-13
7-5
7-3
6-10
6-9
7-5
4-9
6-10
6-9
9-20
4-10
4-12
2-3
2-29
7-6
8-7
7-7
4-13
5-3
2-3
4-9
2-5
4-12
2-5
2-6
2-27
2-22
2-6
4-10
2-6
6-7
2-8
7-6
4-13
to
8-8
2-11
2-28
2-12
4-10
7-15
5-3
2-11
4-3
4-13
Index
4-12
2-11
1-2
4-3
2-28
SEN register
send operations
SENHI register
serial port enable bit
serial ROM download
SFF-8067 interface 2-4, 2-23,
SFF-8067 mode
SHID[2:0] bits 2-6,
single
single-ended mode
SISO bit
slave mode stop bit
slow blink rate bits
soft reset
SPEN bit
SRAM, internal
STA bit 6-5,
start bit 6-5,
start DMA initiator receive register
start DMA target receive register
status register reads register
STO bit 6-6,
stop bit 6-6,
stress ratings
STS bit
SYSCTRL register
system control register
T
T1C register
T1CLR bit
T1EXP bit
T1FC register
T1IEN bit
T1PS bit
T1RUN bit
T1SC register
T1TH register
T2C register
T2CLR bit
T2EXP bit
T2FC register
T2IEN bit
T2PS bit
T2RUN bit
T2SC register
T2T register
T2TH[7:0] bits
target applications
target command register
target mode bit
TC bit
TE bit
TGTM bit
timer 1
chip address mapping
external ROM
selecting a two-wire serial interface
control
interrupts
pin assignments
typical implementation
ended SCSI signals
clear bit
control register
7-6
4-14
6-8
7-6
7-9
7-11
8-8
2-23
7-9
7-11
4-6
7-9
7-8
7-11
7-11
2-25
7-8
7-11
7-9
6-7
6-7
6-7
7-12
6-7
7-8
7-11
4-10
2-31
9-2
7-10
7-9
7-13
7-10
7-12
7-12
4-13
2-4
4-6
2-13
2-24
2-22
2-6
8-7
4-13
8-7
7-8
2-8
6-8
3-18
8-8
to
8-7
9-7
2-26
4-8
2-22
1-3
6-7
2-24
4-12
4-13
2-23
IX-9