LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 89

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

R
IEN
TIP
Register: 0xFC11
DMA Transfer Length (DTL)
Read/Write
DTL
7
0
0
Reserved
Interrupt Enable
When this bit is set to a 1, the DMA function will generate
an interrupt whenever the TIP bit transitions from a 1 to
a 0. This signifies that (1) the transfer completed
normally, or (2) the TIP bit was written to a 0, which
manually interrupted the transfer.
Transfer in Progress
When this bit is written to a 1, the DMA function will begin
a transfer. The transfer length is specified in the
Transfer Length (DTL)
source or destination addresses are specified in the
Source/Destination Low (DSDL)
Source/Destination High (DSDH)
read value of this bit will stay 1 until either (1) the transfer
completes normally, or (2) this bit is written to a 0, which
can only be done when the DMA is not active. While this
bit is 0, the other status bits in this register will be valid
and the DTL register will hold the remaining transfer
count. Conditions for which the SCSI core will interrupt
are discussed in
Data Transfer Length
These register bits store the 8-bit transfer length for the
DMA function. This register should be set to a value
between 0x00 and 0xFF prior to setting bit 0 (TIP) of the
DMA Status (DS)
register to a value of 0 corresponds to a desired transfer
length of 256 bytes. When the transfer ends or is
interrupted, this register will read the value of the number
of bytes remaining in the transfer.
0
0
Chapter
register to initiate a transfer. Setting this
DTL
register (0xFC11) and the data
0
2.
(0xFC12) and
(0xFC13) registers. The
0
0
DMA
DMA
DMA
0
0
[7:0]
4-15
2
1
0