LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 52

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 2.6
2.11 JTAG Boundary Scan Testing
2-34
Number
ISR Bit
3
2
1
0
Timer 2
Timer 1
8067 Port 1 or MPIO3_1
8067 Port 0 or MPIO3_0
Interrupt Handling (Cont.)
Interrupt Source
The LSI53C040 includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification. The device can accept
all required boundary scan instructions, as well as the optional CLAMP,
HIGH-Z, and IDCODE instructions.
The LSI53C040 uses an 8-bit instruction register to support all boundary
scan instructions. The data registers included in the device are the
Boundary Data register, the IDCODE register, and the Bypass register.
The device can handle a 10 MHz TCK frequency for TDO and TDI.
Functional Description
T2C (0xFE09)
T1C (0xFE05)
MPI3
PCST1 (0xFC2A)
MPI3
PCST0 (0xFC22)
determine cause of
Location to read to
interrupt
Programs Timer 2, and
enables an interrupt upon
expiration of the timer.
Programs Timer 1, and
enables an interrupt upon
expiration of the timer.
Reads the values of
MPIO3_[1:0] pins, which also
serve as external interrupt
lines to the microcontroller
core.
Read Interrupt and Write
Interrupt status bits.
Reads the values of
MPIO3_[1:0] pins, which also
serve as external interrupt
lines to microcontroller core.
Read Interrupt and Write
Interrupt status bits.
Description