SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 13

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

Parity, Low Power and Standby with QuadCS Mode Disabled
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
RESET
1
(LOW and HIGH) when RESET is driven HIGH.
2 C/A= DAn, DBAn, DRAS, DCAS, DWE. Inputs DCKEn, DODTn, and DCSn are not included in this range. This
column represents the sum of the number of C/A signals that are electrically HIGH.
3 PAR_IN arrives one clock cycle after the data to which it applies, ERROUT is issued three clock cycles after the
failing data.
4 This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ERROUT is low,
it stays latched low for exactly two clock cycles or until RESET is driven low.
5 Same three cycle delay for ERROUT is valid for the de-select phase (see diagram)
6 The system is not allowed to pull CK and CK low while ERROUT is asserted.
H
H
H
H
H
H
H
H
H
H
H
L
It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels
X or floating X or floating X or floating X or floating
DCS0
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
X
X
X
X
H
X
X
L
L
L
L
DCS1
X
X
X
X
H
X
X
L
L
L
L
L or H
CK
Inputs
↑
↑
↑
↑
↑
↑
↑
↑
↑
L
1
H or L
CK
↓
↓
↓
↓
↓
↓
↓
↓
↓
L
1
X or floating
Σ of C/A
Even
Even
Even
Even
Odd
Odd
Odd
Odd
X
X
X
13
2
X or floating
PAR_IN
COMMERCIAL TEMPERATURE RANGE
H
H
H
H
X
X
X
L
L
L
L
SSTE32882KA1
3
ERROUT
ERROUT
Output
H
H
H
H
H
H
H
L
L
L
L
5
6
0
4
7314/8