SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 43

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

POWER SAVING MODES
REGISTER CKE POWER DOWN
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
1 CK left out for better visibility.
The device supports different power saving mechanisms.
When both inputs CK and CK are being held low the device stops operation and enters low-power static and standby operation.
It stops its PLL and floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1 which are kept driven low. Before
the device is taken out of standby operation by applying a stable input clock signal, the register inputs DCS[n:0] must be pulled
high to prevent accidential access to the control registers and DCKE0 as well as DCKE1 must be pulled low for a certain period
of time (t
clocks (CK = CK = low) will only put the SSTE32882KA1 in low-power mode and will not clear the content of the control
words. The control words will reset only when RESET is diven low.
A float feature can be enabled by setting the corresponding bit in the control register. This causes the device to monitor all the
DCS[n:0] inputs and to float all outputs corresponding with the chip select gated inputs when all the DCS[n:0] inputs are high.
If any one of the DCS[n:0] inputs are low, the Qn outputs will function normally.
Once all the DCS[n;0] inputs are high, the gated address command inputs to the register can float to conserve input termination
power. DCKE0, DCKE1, DODT0 and DODT1 need to be driven by the system all the time.
The RESET input has priority over all other power saving mechanisms. When RESET is driven low, it will force the Qn
outputs to float, the ERROUT output high, the QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs low, and disables Input
Bus Termination (IBT).
If RC9[DBA1] is set to “1”, the SSTE32882KA1 monitors both DCKEn input signals and enters into power saving state when
it latches Low on both DCKEn inputs and at least one of the DCKEn input has transitioned from High to Low. If any input
Chip Select signal (DCS[n:0]) is asserted together with DCKEn, the SSTE32882KA1 transfers the corresponding command to
its outputs together with QxCKEn Low.
There are two modes of CKE Power Down selected by RC9. Bit DBA0 in RC9 indicates whether the register turns off IBT or
keeps IBT on.
Input
ERROUT
PAR_IN
ACT
DCS0
DCS1
CK
CA
(1)
). The input clock must be stable for a time (t
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
n
CA0
Parity-Error Occurrences During Control Word Programming
n+1
CA1
P0
n+2
CA2
P1
n+3
CA3
ERROUTresulting from CA0 - P0, followed by 2nd error during control word access in CA3 - P3
P2
n+4
CA4
P3
STAB
n+5
CA5
P4
) before any access to the device takes place. Stopping the
n+6
P5
43
n+7
n+8
COMMERCIAL TEMPERATURE RANGE
n+9
SSTE32882KA1
7314/8