SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 20

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

Thermal
DC Current Specifications
Operating Electrical Characteristics
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Symbol
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
I
I
I
I
CCD
I
DD 6
OH
OL
1
operation. The differential inputs must not be floating unless RESET is LOW.
2
3
4
5
6
0.
T
I
ID
I
case (max)
Symbol
1 Measurement procedure JESD51-2
2 This spec is meant to guarantee a Tj of 125C by the SSTE32882KA1 device. Since Tj cannot be measured or observed by users, Tcase is specified instead.
Under all thermal condition, the Tj of a SSTE32882KA1 device shall not be higher than 125
The RESET and MIRROR inputs of the device must be held at valid voltage levels (not floating) to ensure proper device
All typical values are at V
DCKEn, DODTn, DAn, DBAn, DRAS, DCAS, DWE, DCSn, PAR_IN are measured while RESET is pulled LOW.
The CK and CK inputs have pull-down resistors in the range of 10KΩ to 100KΩ.
Qn = QxAn, QxCSn, QxCKEn, QxODTn, QxRAS, QxCAS, QxWE, and QxBAn.
The supply current is measured as the total current consumptoion on the AV
Input current
QCSEN input current
Input current
HIGH-level output current
LOW-level output current
Static standby current
Low-Power Static Operating
Dynamic operating -- input clock
only; active outputs
Dynamic operating -- per each data
input
Case temperature
Parameter
Parameter
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
1
1
DD
DDR3/DDR3L/
= 1.5V, T
DDR3U
-800
109
2
RESET, MIRROR, V
QCSEN, V
Data inputs
CK, CK
Qn
Yn, Yn, FBOUT, FBOUT
Qn
Yn, Yn, FBOUT, FBOUT
ERROUT
RESET = GND and CK = CK = V
RESET = V
V
RESET = V
V
switching 50% duty cycle, I
H. V
RESET = V
V
data input switching at one half clock frequency, 50%
duty cycle; RC0[DBA0]=0, RC0[DBA1]=0, I
DCS0 = L, DCS1 = H. V
IL
IL
DD
A
5
5
(
(
AC
AC
, RC8=
DD
= 25°C.
), RC0[DBA0]=0, RC0[DBA1]=0, CK and CK
), CK and CK switching 50% duty cycle. One
4
= V
; V
DDR3/DDR3L
I
3
X
I
DD
DD
DD
DDMAX
= V
, V
/DDR3U
= V
111,IBT
-1066
, MIRROR = V
, MIRROR = V
I
and CK = CK = V
108
DD
= V
DD
2
or GND
DD
or GND
I
Conditions
OFF
= V
or GND
DD
DD
O
= V
DDR3/DDR3L/
= 0, DCS0 = L, DCS1 =
or GND
DD
DD
DDR3U-1333
o
DDMAX
C.
, V
, V
IL
IL
(
106
I
I
(
AC
AC
= V
= V
2
), MIRROR =
)
IH
IH
DD
(
(
20
AC
AC
O
, PV
) or
) or
= 0,
DDR3/DDR3L
DD
/DDR3U
, and V
-1600
103
2
Min
-150
COMMERCIAL TEMPERATURE RANGE
-11
-11
11
11
25
-5
DD
SSTE32882KA1
supply current pins. Io =
Typ
--
--
DDR3-1866
2
101
Max
2
150
±5
±5
15
5
5
μA/Clock
μA/MHz
D Input
MHz/
Unit
o
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
C
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