SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 42

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SSTE32882KA1AKG

Manufacturer Part Number
SSTE32882KA1AKG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of SSTE32882KA1AKG

Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTE32882KA1AKG
Manufacturer:
IDT
Quantity:
20 000
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences; during chip-select and chip-deselect modes. The
diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+1 input clock cycles (PAR_IN
clocked in on the n+1 and n+2 input clock cycles). Parity error in the chip-select mod is detected, but parity error in the
chip-deselect mode is ignored.
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences; during normal operation and during control
register programming. The diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+3 input
clock cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles). The data on the n+3 input clock pulse is intended for
the control mode register. Parity error during control mode register programming is detected and the parity functionality is the
same as during normal operation. If a parity error occurs, the command is ignored.
Input
Input
ERROUT
ERROUT
PAR_IN
PAR_IN
DCSx
CK
CK
CA
CA
(1)
(1)
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Two Parity-Error Occurrences Separated by two Clock Cycles of no Error Occurrence
CA0
n
CA0
n
n+1
CA1
P0
Parity-Error Occurrence In Chip-Deselect Mode
n+2
CA2
P1
ERROUT resulting from CA0 - P0, followed by 2nd error in CA3 - P3
n+1
CA1
P0
n+3
CA3
P2
n+2
CA2
P1
ERROUT resulting from CA0 - P0, subsequent parity errors during DCSx high ignored
n+4
CA4
P3
n+5
CA5
P4
n+3
P2
n+6
P5
n+4
42
n+7
n+8
n+5
COMMERCIAL TEMPERATURE RANGE
n+9
SSTE32882KA1
n+6
7314/8

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